am45dl3208g Advanced Micro Devices, am45dl3208g Datasheet - Page 60

• Manufacturer Part Number: am45dl3208g
• Description: Stacked Multi-chip Package Mcp Flash Memory And Sram
• Manufacturer: Advanced Micro Devices

Pseudo SRAM AC CHARACTERISTICS
Notes:
1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. t
3. t
4. t
5. A write occurs during the overlap (t
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asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
Address
CE1#s
CE2s
UB#s, LB#s
WE#
Data In
Data Out
Figure 32. Pseudo SRAM Write Cycle—CE1#s Control
WP
) of low CE1#s and low WE#. A write begins when CE1#s goes low and WE# goes low when
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P R E L I M I N A R Y
t
AS
(See Note 2 )
Am45DL3208G
(See Note 3)
WR
applied in case a write ends as CE1#s or WE# going high.
t
t
AW
CW
t
(See Note 5)
WC
t
BW
t
WP
t
DW
Data Valid
WP
is measured from the beginning of write
t
WR
t
DH
(See Note 4)
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March 12, 2004