am45dl3208g Advanced Micro Devices, am45dl3208g Datasheet - Page 5

• Manufacturer Part Number: am45dl3208g
• Description: Stacked Multi-chip Package Mcp Flash Memory And Sram
• Manufacturer: Advanced Micro Devices

TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Flash Command Definitions . . . . . . . . . . . . . . . . 27
Flash Write Operation Status . . . . . . . . . . . . . . . . 33
March 12, 2004
Special Package Handling Instructions .................................... 7
Word/Byte Configuration ........................................................ 13
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Standby Mode ........................................................................ 14
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Sector/Sector Block Protection and Unprotection .................. 19
Write Protect (WP#) ................................................................ 20
Temporary Sector Unprotect .................................................. 20
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
Hardware Data Protection ...................................................... 23
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 27
Byte/Word Program Command Sequence ............................. 28
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
DQ7: Data# Polling ................................................................. 33
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
PSRAM Byte Mode, CIOs = V
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
PSRAM Word Mode, CIOs = V
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
PSRAM Byte Mode, CIOs = V
Accelerated Program Operation .......................................... 14
Autoselect Functions ........................................................... 14
Table 5. Top Boot Sector Addresses .............................................15
Table 7. Bottom Boot Sector Addresses .........................................17
Table 9. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Table 10. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
Figure 3. SecSi Sector Protect Verify.............................................. 23
Low V
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Unlock Bypass Command Sequence .................................. 28
Figure 4. Program Operation .......................................................... 29
Figure 5. Erase Operation............................................................... 30
CC
Write Inhibit ........................................................... 23
SS
SS
CC
....................................................11
....................................................13
..................................................12
P R E L I M I N A R Y
SS
IL
IH
Am45DL3208G
;
;
;
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 37
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 38
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Flash Erase And Programming Performance . . 60
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 60
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 60
RY/BY#: Ready/Busy# ............................................................ 34
DQ6: Toggle Bit I .................................................................... 34
DQ2: Toggle Bit II ................................................................... 35
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
CMOS Compatible .................................................................. 38
Pseudo SRAM CE#s Timing ................................................... 42
Read-Only Operations ........................................................... 43
Hardware Reset (RESET#) .................................................... 44
Word/Byte Configuration (CIOf) .............................................. 45
Flash Erase and Program Operations .................................... 46
Temporary Sector Unprotect .................................................. 51
Alternate CE#f Controlled Erase and Program Operations .... 53
Power Up Time ....................................................................... 55
Read Cycle ............................................................................. 55
Read Cycle ............................................................................. 56
Write Cycle ............................................................................. 57
Figure 6. Data# Polling Algorithm .................................................. 33
Figure 7. Toggle Bit Algorithm........................................................ 34
Table 17. Write Operation Status ................................................... 36
Figure 8. Maximum Negative Overshoot Waveform ...................... 37
Figure 9. Maximum Positive Overshoot Waveform........................ 37
Figure 10. I
Automatic Sleep Currents) ............................................................. 39
Figure 11. Typical I
Figure 12. Test Setup.................................................................... 41
Figure 13. Input Waveforms and Measurement Levels ................. 41
Figure 14. Timing Diagram for Alternating
Between Pseudo SRAM and Flash................................................ 42
Figure 15. Read Operation Timings ............................................... 43
Figure 16. Reset Timings ............................................................... 44
Figure 17. CIOf Timings for Read Operations................................ 45
Figure 18. CIOf Timings for Write Operations................................ 45
Figure 19. Program Operation Timings.......................................... 47
Figure 20. Accelerated Program Timing Diagram.......................... 47
Figure 21. Chip/Sector Erase Operation Timings .......................... 48
Figure 22. Back-to-back Read/Write Cycle Timings ...................... 49
Figure 23. Data# Polling Timings (During Embedded Algorithms). 49
Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 50
Figure 25. DQ2 vs. DQ6................................................................. 50
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 51
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 52
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
Figure 29. Pseudo SRAM Read Cycle—Address Controlled......... 55
Figure 30. Pseudo SRAM Read Cycle........................................... 56
Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 57
Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 58
Figure 33. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 59
CC1
Current vs. Time (Showing Active and
CC1
vs. Frequency............................................ 39
3