am45dl3208g Advanced Micro Devices, am45dl3208g Datasheet - Page 15

• Manufacturer Part Number: am45dl3208g
• Description: Stacked Multi-chip Package Mcp Flash Memory And Sram
• Manufacturer: Advanced Micro Devices

Legend: L = Logic Low = V
Input, Byte Mode, SADD = Flash Sector Address, A
Data Out
Notes:
1. Other operations except for those indicated in this column are inhibited.
2. Do not apply CE#f = V
3. Don’t care or open LB#s or UB#s.
4. If WP#/ACC = V
5. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
6. If WP#/ACC = V
FLASH DEVICE BUS OPERATIONS
Word/Byte Configuration
The CIOf pin controls whether the device data I/O pins
operate in the byte or word configuration. If the CIOf
pin is set at logic ‘1’, the device is in word configura-
tion, DQ15–DQ0 are active and controlled by CE#f
and OE#.
If the CIOf pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
March 12, 2004
Operation
(Notes 1, 2)
Read from Flash
Write to Flash
Standby
Output Disable
Flash Hardware
Reset
Sector Protect
(Note 5)
Sector Unprotect
(Note 5)
Temporary
Sector Unprotect
Read from SRAM
Write to SRAM
If WP#/ACC = V
Block Protection and Unprotection”.
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection and
Unprotection”. If WP#/ACC = V
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
V
ACC
0.3 V
IL
IL
CE#f CE1#s CE2s OE# WE#
, the two outermost boot sectors remain protected. If WP#/ACC = V
CC
, the boot sectors will be protected. If WP#/ACC = V
H
H
H
L
L
X
L
L
X
(9V), the program time will be reduced by 40%.
±
IL
, CE1#s = V
IL
, H = Logic High = V
H
X
H
X
H
X
H
X
H
X
H
X
H
X
L
L
L
HH,
X
X
X
H
X
X
X
X
H
H
all sectors will be unprotected.
L
L
L
L
L
L
L
IL
and CE2s = V
H
H
H
H
L
X
X
X
L
X
P R E L I M I N A R Y
IH
H
X
H
X
X
H
L
L
L
L
, V
IN
ID
IH
= Address In (for Flash Byte Mode, DQ15 = A-1), D
SA
SA
SA
SA
Am45DL3208G
= 11.5–12.5 V, V
X
X
X
X
X
X
X
at the same time.
A1 = H,
A1 = H,
A6 = L,
A6 = L,
SADD,
SADD,
A0 = L
A0 = L
Addr.
A
A
A
A
A
X
X
X
IN
IN
IN
IN
IN
active and controlled by CE#f and OE#. The data I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE#f and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
(Note 3)
IH
LB#s
HH
the boot sectors protection will be removed.
X
X
X
X
X
X
X
X
X
X
= 9.0 ± 0.5 V, X = Don’t Care, SA = PSRAM Address
(Note 3)
IL
UB#s
; PSRAM Byte Mode, CIOs = V
X
X
X
X
X
X
X
X
X
X
IH
, the two outermost boot sector protection
RESET#
V
0.3 V
V
V
V
CC
I H
H
H
H
H
H
L
ID
ID
ID
. The CIOf pin determines
±
WP#/ACC
(Note 6)
(Note 6)
(Note 4)
(Note 3)
L/H
L/H
L/H
L/H
H
X
X
IL
IN
. CE#f is the power
= Data In, D
High-Z
High-Z
High-Z
DQ7–
D
D
DQ0
D
D
D
D
D
OUT
OUT
IN
IN
IN
IN
IN
SS
DQ15–
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
OUT
DQ8
X
X
=
13