am45dl3208g Advanced Micro Devices, am45dl3208g Datasheet - Page 38

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am45dl3208g

Manufacturer Part Number
am45dl3208g
Description
Stacked Multi-chip Package Mcp Flash Memory And Sram
Manufacturer
Advanced Micro Devices
Datasheet
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
36
Standard
Suspend
Mode
Erase
Mode
Refer to the section on DQ5 for more information.
details.
is in progress. The device outputs array data if the system addresses a non-busy bank.
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-Suspend-Program
Erase-Suspend-
Read
Status
Erase
Suspended Sector
Non-Erase
Suspended Sector
Table 17. Write Operation Status
P R E L I M I N A R Y
(Note 2)
Am45DL3208G
DQ7#
DQ7#
Data
DQ7
0
1
No toggle
Toggle
Toggle
Toggle
Data
DQ6
(Note 1)
Data
DQ5
0
0
0
0
Data
DQ3
N/A
N/A
N/A
1
No toggle
(Note 2)
Toggle
Toggle
DQ2
Data
N/A
March 12, 2004
RY/BY#
0
0
1
1
0

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