s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 88

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s71ws256jc0

Manufacturer Part Number
s71ws256jc0
Description
Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
Manufacturer
Meet Spansion Inc.
Datasheet
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
3. When reading write operation status bits, the system must always provide the bank address where the Embedded
4. The system may read either asynchronously or synchronously (burst) while in erase suspend.
5. The RDY pin acts a dedicated output to indicate the status of an embedded erase or program operation is in progress. This
6. When the device is set to Asynchronous mode, these status flags should be read by CE# toggle.
86
Standard
Suspend
Erase
Refer to the section on DQ5 for more information.
details.
Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
is available in the Asynchronous mode only.
Mode
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-Suspend-
Read
Erase-Suspend-Program
(Note
4)
Status
Erase
Suspended Sector
Non-Erase Suspended
Sector
Table 15.2 Write Operation Status
S29WS128J/064J
(Note
DQ7#
DQ7#
Data
DQ7
0
1
D a t a
2)
No toggle
(Note
Toggle
Toggle
Toggle
Data
DQ6
S h e e t
6)
(Note
Data
DQ5
0
0
0
0
1)
Data
DQ3
N/A
N/A
N/A
1
No toggle
(Note
(Note
Toggle
Toggle
Data
DQ2
N/A
S29WS-J_M0_A4 June 24, 2005
6)
2)
High Impedance
High Impedance
RDY
(Note
0
0
0
5)

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