s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 163

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Notes:
1. Non-default BCR settings: Latency code two (three clocks); Wait active Low; Wait asserted during delay.
2. When transitioning between asynchronous and variable-latency burst operations, CE# must go High. If CE# goes High, it
162
DQ[15:0]
LB#/UB#
must remain High for at least 5ns (t
A[22:0]
ADV#
WAIT
WE#
OE#
CE#
CLK
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V IH
V IL
V OH
V OL
V IH
V IL
High-Z
t WHZ
Address
Valid
t WC
Figure 33.18 Asynchronous Write (ADV# Low) Followed By Burst Read
t CW
t WP t WPH
DATA
t DH
t WC
t AW
t BW
Address
t DW
Valid
DATA
t WC
t WR
CBPH
) to schedule the appropriate internal refresh operation.
(Note 2)
t CKA
t CSP
A d v a n c e
CellularRAM Type 2
t CSP
t SP
Address
t SP
t SP
t SP
V OH
V OL
Valid
t HD
t HD
t HD
t HD
High-Z
t CEW
t CLK
I n f o r m a t i o n
t BOE
t ACLK
Output
Valid
t KOH
Output
Valid
Legend:
Output
Valid
Don't Care
CellRam_03_A0 March 9, 2005
Output
Valid
t OHZ
Undefined
High-Z