s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 31

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

11.2
June 24, 2005 S29WS-J_M0_A4
Requirements for Synchronous (Burst) Read Operation
The device is capable of continuous sequential burst operation and linear burst operation of a pre-
set length. When the device first powers up, it is enabled for asynchronous read operation.
Prior to entering burst mode, the system should determine how many wait states are desired for
the initial word (t
of the clock will be the active clock edge, and how the RDY signal will transition with valid data.
The system would then write the configuration register command sequence. See “Set Configura-
tion Register Command Sequence” section on page 63 and “Command Definitions” section on
page 63 for further details.
Once the system has written the “Set Configuration Register” command sequence, the device is
enabled for synchronous reads only.
The initial word is output t
output t
the internal address counter. Note that the device has a fixed internal address boundary that oc-
curs every 64 words, starting at address 00003Fh.
During the time the device is outputting data at this fixed internal address boundary (address
00003Fh, 00007Fh, 0000BFh, etc.), a two cycle latency (66MHz) or a three cycle latency(80MHz)
occurs before data appears for the next address (address 000040h, 000080h, 0000C0h, etc.).
Additionally, when the device is read from an odd address, one wait state is inserted when the
address pointer crosses the first boundary that occurs every 16 words. For instance, if the device
is read from 000011h, 000013h, … ,00001Fh (odd), one wait state is inserted before the data of
000020h is output. This wait is inserted only at the boundary of the first 16 words. Then, if the
device is read from the odd address within the last 16 words of 64 word boundary (address
000031h,000033h, … , 00003Fh), a three-cycle latency occurs before data appears for the next
address (address 000040h). During the boundary crossing condition, the system must assert an
additional wait state for WS128J model numbers 10 and 11.
The RDY output indicates this condition to the system by pulsing deactive (low). See
Figure 22.23, “Latency with Boundary Crossing,” on page
The device will continue to output sequential burst data, wrapping around to address 000000h
after it reaches the highest addressable memory location, until the system drives CE# high, RE-
SET# low, or AVD# low in conjunction with a new address. See
Operations,” on page
If the host system crosses the bank boundary while reading in burst mode, and the device is not
programming or erasing, a two-cycle latency will occur as described above in the subsequent
bank. If the host system crosses the bank boundary while the device is programming or erasing,
the device will provide read status information. The clock will be ignored. After the host has com-
pleted status reads, or the device has completed the program or erase operation, the host can
restart a burst operation using a new address and AVD# pulse.
8-, 16-, and 32-Word Linear Burst with Wrap Around
The remaining three burst read modes are of the linear wrap around design, in which a fixed num-
ber of words are read from consecutive addresses. In each of these modes, the burst addresses
read are determined by the group within which the starting address falls. The groups are sized
according to the number of words read in a single burst sequence for a given mode (see
Table
11.2.)
BACC
after the active edge of each successive clock cycle, which automatically increments
IACC
D a t a
) of each burst access, what mode of burst operation is desired, which edge
28.
IACC
after the active edge of the first CLK cycle. Subsequent words are
S h e e t
S29WS128J/064J
108.
Table 11.1, “Device Bus
29