s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 67

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

June 24, 2005 S29WS-J_M0_A4
14.2.3
Notes:
1.
2.
It is recommended that the wait state command sequence be written, even if the default wait
state value is desired, to ensure the device is set as expected. A hardware reset will set the wait
state to the default setting.
Standard wait-state Handshaking Option
The host system must set the appropriate number of wait states in the flash device depending
upon the clock frequency. The host system should set address bits A14–A12 to 010 for a clock
frequency of 66/80 MHz for the system/device to execute at maximum speed.
Table 14.2
conditions.
Notes:
1.
2.
The host system must set the appropriate number of wait states in the flash device depending
upon the clock frequency. Note that the host system must set again the number of wait state
when the host system change the clock frequency. For example, the host system must set from
6 or 7 wait state to less than 5 wait states when the host system change the clock frequency from
80MHz to less than 80MHz. The autoselect function allows the host system to determine whether
the flash device is enabled for handshaking. See the “Autoselect Command Sequence” section on
page 68 for more information.
8-Word or 16-Word or Continuous
32-Word
Upon power-up or hardware reset, the default setting is seven wait states.
RDY will default to being active with data when the Wait State Setting is set to a
total initial access cycle of 2.
In the 8-, 16- and 32-word burst read modes, the address pointer does not cross
64-word boundaries (addresses which are multiples of 3Fh).
For WS128J model numbers 10 and 11, an additional clock cycle is required for
boundary crossings while in Continuous read mode.
A14
0
0
0
0
1
1
1
1
Table 14.2 Wait States for Standard wait-state Handshaking
describes the recommended number of clock cycles (wait states) for various
Table 14.1 Programmable Wait State Settings
Burst Mode
D a t a
A13
0
0
1
1
0
0
1
1
S h e e t
S29WS128J/064J
A12
0
1
0
1
0
1
0
1
Typical No. of Clock Cycles after AVD# Low
66 MHz
Total Initial Access Cycles
4
5
7 (default)
Reserved
Reserved
2
3
4
5
6
80 MHz
6 or 7
7
65