s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 142

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Notes:
1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. High-Z to Low-Z timings are tested with the circuit shown in
3. Low-Z to High-Z timings are tested with the circuit shown in
March 9, 2005 CellRam_03_A0
away from the High-Z (V
from either V
Chip Disable to DQ and Wait High-Z Output
OH
LB#/UB# Disable to DQ High-Z Output
Output Disable to DQ High-Z Output
or V
Output Hold from Address Change
LB#/UB# Enable to Low-Z Output
Output Enable to Low-Z Output
Address Hold from ADV# High
Output Enable to Valid Output
Address Setup to ADV# High
Chip Enable to Low-Z Output
OL
Maximum CE# Pulse Width
Chip Select Access Time
CE# Low to ADV# High
ADV# Pulse Width High
ADV# Pulse Width Low
LB#/UB# Access Time
CE# Low to Wait Valid
toward V
Address Access Time
Table 32.3 Asynchronous Read Cycle Timing Requirements
ADV# Access Time
CC
Page Access Time
Read Cycle Time
Page Cycle Time
A d v a n c e
Q/2) level toward either V
Parameter
CC
Q/2.
I n f o r m a t i o n
CellularRAM Type 2
OH
or V
OL
Figure
Figure
.
32.2. The Low-Z timings measure a 100mV transition
32.2. The High-Z timings measure a 100mV transition
Symbol
t
t
t
t
t
t
t
t
t
t
AADV
t
t
t
t
t
t
t
t
CEW
t
t
t
t
AVH
BHZ
CEM
CVS
OHZ
APA
AVS
BLZ
OLZ
VPH
CO
OH
AA
BA
HZ
OE
PC
RC
VP
LZ
Min
10
10
10
10
20
70
10
10
5
1
5
5
70ns
Max
7.5
70
70
20
70
70
20
8
8
8
8
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4
3
4
3
4
3
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