s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 123

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

27.2 Page Mode Read Operation
27.3 Burst Mode Operation
122
ADDRESS
LB#/UB#
DATA
WE#
OE#
CE#
Page mode is a performance-enhancing extension to the legacy asynchronous Read operation. In
page mode-capable products, an initial asynchronous Read access is performed, then adjacent
addresses can be Read quickly by simply changing the low-order address. Addresses A[3:0] are
used to determine the members of the 16-address CellularRAM page. Addresses A[4] and higher
must remain fixed during the entire page mode access.
mode access. Page mode takes advantage of the fact that adjacent addresses can be Read in a
shorter period of time than random addresses. Write operations do not include comparable page
mode functionality.
During asynchronous page mode operation, the CLK input must be static (HIGH or LOW - no tran-
sitions). CE# must be driven High upon completion of a page mode access. WAIT is driven while
the device is enabled and its state should be ignored. Page mode is enabled by setting RCR[7] to
High. ADV must be driven Low during all page mode Read accesses. The CE# LOW time is limited
by refresh considerations. CE# must not stay LOW longer than t
Burst mode operations enable High-speed synchronous Read and Write operations. Burst opera-
tions consist of a multi-clock sequence that must be performed in an ordered fashion. After CE#
goes Low, the address to access is latched on the rising edge of the next clock that ADV# is Low.
During this first clock rising edge, WE# indicates whether the operation is going to be a Read
(WE# = High,
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length
bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a
specified address and burst through the entire memory.
The latency count stored in the BCR defines the number of clock cycles that elapse before the
initial data value is transferred between the processor and CellularRAM device.
The WAIT output is asserted as soon as CE# goes LOW, and is de-asserted to indicate when data
is to be transferred into (or out of) the memory. WAIT is again asserted if the burst crosses the
boundary between 128-word rows. Once the CellularRAM device has restored the previous row's
Figure 27.3 Page Mode Read Operation (ADV# Low)
Figure
27.4) or Write (WE# = Low,
ADD[0]
t AA
A d v a n c e
CellularRAM Type 2
D[0]
ADD[1]
t APA
I n f o r m a t i o n
D[1]
ADD[2]
Figure
t APA
Figure 27.3
27.5).
D[2]
ADD[3]
t APA
CEM
.
D[3]
shows the timing for a page
CellRam_03_A0 March 9, 2005
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