s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 32

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

11.3
11.4
11.5
11.6
30
Configuration Register
Handshaking
Simultaneous Read/Write Operations with Zero Latency
Writing Commands/Command Sequences
As an example: if the starting address in the 8-word mode is 39h, the address range to be read
would be 38-3Fh, and the burst sequence would be 39-3A-3B-3C-3D-3E-3F-38h-etc. The burst
sequence begins with the starting address written to the device, but wraps back to the first ad-
dress in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes
begin their burst sequence on the starting address written to the device, and then wrap back to
the first address in the selected address group. Note that in these three burst read modes
the address pointer does not cross the boundary that occurs every 128 or 64 words;
thus, no wait states are inserted (except during the initial access).
The RDY pin indicates when data is valid on the bus.
The device uses a configuration register to set the various burst parameters: number of wait
states, burst read mode, active clock edge, RDY configuration, and synchronous mode active.
The device is equipped with a handshaking feature that allows the host system to simply monitor
the RDY signal from the device to determine when the initial word of burst data is ready to be
read. The host system should use the programmable wait state configuration to set the number
of wait states for optimal burst mode operation. The initial word of burst data is indicated by the
active edge of RDY after OE# goes low.
For optimal burst mode performance, the host system must set the appropriate number of wait
states in the flash device depending on clock frequency. See “Set Configuration Register Com-
mand Sequence” section on page 63 for more information.
This device is capable of reading data from one bank of memory while programming or erasing
in another bank of memory. An erase operation may also be suspended to read from or program
to another location within the same bank (except the sector being erased).
to-Back Read/Write Cycle Timings,” on page 111
ated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-
while-program and read-while-erase current specifications.
The device has the capability of performing an asynchronous or synchronous write operation.
While the device is configured in Asynchronous read mode, it is able to perform Asynchronous
write operations only. CLK is ignored in the Asynchronous programming mode. When in the Syn-
chronous read mode configuration, the device is able to perform both Asynchronous and
Synchronous write operations. CLK and WE# address latch is supported in the Synchronous pro-
gramming mode. During a synchronous write operation, to write a command or command
sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V
vice, and drive WE# and CE# to V
asynchronous write operation, the system must drive CE# and WE# to V
16-word
32-word
8-word
Mode
Group Size
16 words
32 words
8 words
Table 11.2 Burst Address Groups
S29WS128J/064J
Group Address Ranges
00-1Fh, 20-3Fh, 40-5Fh,...
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
IL
, and OE# to V
D a t a
IL
, and OE# to V
S h e e t
shows how read and write cycles may be initi-
IH
. when writing commands or data. During an
IH
when providing an address to the de-
IL
and OE# to V
Figure 22.26, “Back-
S29WS-J_M0_A4 June 24, 2005
IH
when