s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 116

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Features
! Single device supports asynchronous, page,
! V
! Random Access Time: 70 ns
! Burst Mode Write Access
! Burst Mode Read Access
! Page Mode Read Access
General Description
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do
not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
CellularRAM Type 2
64 Megabit
Burst CellularRAM
and burst operations
— 1.70 V–1.95 V V
— 1.70 V–3.30 V V
— Continuous burst
— 4, 8, or 16 words, or continuous burst
CellularRAM™ products are High-speed, CMOS dynamic random access memories developed for low-
power, portable applications. These devices include an industry standard burst mode Flash interface that
dramatically increases Read/Write bandwidth compared with other low-power SRAM or Pseudo SRAM
offerings.
To operate seamlessly on a burst Flash bus, CellularRAM products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and
has no significant impact on device Read/Write performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) de-
fines how the CellularRAM device interacts with the system memory bus and is nearly identical to its
counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to control how
refresh is performed on the DRAM array. These registers are automatically loaded with default settings
during power-up and can be updated anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. CellularRAM prod-
ucts include three mechanisms to minimize standby current. Partial array refresh (PAR) enables the
system to limit refresh to only that part of the DRAM array that contains essential data. Temperature com-
pensated refresh (TCR) adjusts the refresh rate to match the device temperature—the refresh rate
decreases at lower temperatures to minimize current consumption during standby. Deep power-down
(DPD) enables the system to halt the refresh operation altogether when no vital information is stored in
the device. The system-configurable refresh mechanisms are accessed through the RCR.
CC
, V
CCQ
Voltages
Publication Number CellRam_03
CC
CCQ
Revision A
! Low-Power Consumption
! Low-Power Features
Amendment 0
— Sixteen-word page size
— Interpage Read access: 70ns
— Intrapage Read access: 20ns
— Asynchronous Read < 25 mA
— Intrapage Read < 15 mA
— Initial access, burst Read < 35 mA
— Continuous burst Read < 15m A
— Standby: 120 µA
— Deep power-down < 10 µA
— Temperature Compensated Refresh (TCR)
— Partial Array Refresh (PAR)
— Deep Power-Down (DPD) Mode
Issue Date March 9, 2005
INFORMATION
ADVANCE