s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 177

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

39 Configuration Register Operation
39.1
39.2 Software Access to the Configuration Register
176
Access Using ZZ#
The Configuration Register (CR) defines how the CellularRAM device performs its transparent self-
refresh. Altering the refresh parameters can dramatically reduce current consumption during
standby mode. Page mode control is also embedded into the CR. This register can be updated any
time while the device is operating in a standby state.
trol bits used in the CR. At power up, the CR is set to 0010h.
The CR can be loaded using a WRITE operation immediately after ZZ# makes a HIGH-to-LOW
transition
rising edge of CE# or WE#, whichever occurs first. LB#/UB# are “Don’t Care.” Access using ZZ#
is WRITE only.
The contents of the CR can either be read or modified using a software sequence. The nature of
this access mechanism may eliminate the need for the ZZ# ball.
If the software mechanism is used, ZZ# can simply be tied to V
for ZZ# control purposes is no longer required. However, ZZ# should not be tied to V
system uses DPD; DPD cannot be enabled or disabled using the software access sequence.
The CR is loaded using a four-step sequence consisting of two READ operations followed by two
WRITE operations (see
chronous READ is performed during the fourth operation (see
READ cycle of the highest address cancels the access sequence until a different address is read.
The address used during all READ and WRITE operations is the highest address of the CellularRAM
device being accessed (1FFFFFh for 32 Mb and FFFFFh for 16 Mb); the content of this address is
changed by using this sequence (note that this is a deviation from the CellularRAM specification).
The data bus is used to transfer data into or out of bits 15–0 of the CR.
Writing to the CR using the software sequence modifies the function of the ZZ# ball. Once the
software sequence loads the CR, the level of the ZZ# ball no longer enables PAR operation. PAR
operation is updated whenever the software sequence loads a new value into the CR. This ZZ#
functionality continues until the next time the device is powered-up. The operation of the ZZ#
ball is not affected if the software sequence is only used to read the contents of the CR. The use
of the software sequence does not affect the ability to perform the standard (ZZ#-controlled)
method of loading the CR.
(Figure
39.1). The values placed on addresses A[20:0] are latched into the CR on the
ADDRESS
Figure 39.1 Load Configuration Register Operation
Figure
WE#
CE#
ZZ#
Aysnc/Page CellularRAM Type 2
A d v a n c e
39.2). The read sequence is virtually identical except that an asyn-
t < 500ns
ADDRESS VALID
I n f o r m a t i o n
Figure 39.4 on page 178
CCQ
Figure
. The port line typically used
39.3). Note that a third
CellRAM_05_A0 August 25, 2005
describes the con-
CCQ
if the