m28333-3x Mindspeed Technologies, m28333-3x Datasheet - Page 35

• Manufacturer Part Number: m28333-3x
• Description: Single/dual/triple E3/ds3/sts-1 Line Interface Unit
• Manufacturer: Mindspeed Technologies

M28331/M28332/M28333 (–3x)
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.3.4 The PLL Clock Recovery Circuit
2.3.5 Receive Loss Of Signal (RLOS) Detector
Table 2-3. RLOS Threshold Settings
2.3.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector
28333-DSH-003-A
RLOSMAX
0
0
1
RLOSTHR
0
1
x
The clock recovery circuit (RX PLL) extracts the embedded clock from the sliced
data and provides this clock and the retimed data to the decoder (data mode).
Upon startup (after the internal reset is deasserted), the RX PLL uses a reference
clock (REFCLK) and a phase-frequency detector to lock to the correct data rate
(reference mode). During reference mode, the data outputs are squelched (set to
0). The RX PLL is kept in reference mode until a valid input is detected.
The RLOS detector circuitry consists of 2 functional blocks: the analog section
and the digital. The analog section consists of high-speed, low-offset comparators
used for amplitude qualification. The digital block qualifies the pulse stream 1s
density and zero run length.
comparator levels for each channel (see
RLOS should disable data squelching:
described above) have been received for 128 REFCLKs. The digital block clears
the RLOS when the valid pulse density exceeds 20.3% with less than 64
consecutive zeros during an 128-symbol period.
In the M2833i device, when ENDECDIS = 0 (encoder/decoder enabled), the
decoder takes the output from the clock recovery circuit and decodes the data
(HDB3 or B3ZS) into a single retimed NRZ data signal. The data signal is then
sent out of the M2833i over the RNRZ (RPOS) pin. Any detected Line Code
Violations (LCV) are sent out over the corresponding RLCV (RNEG) pin. The
RLCV pin is asserted for one symbol period at the time the violation appears on
the RX output pin (RNRZ).
Two control pins, RLOSMAX and RLOSTHR, select the trip and hysteresis
A control pin for each channel, RLOSMDIS, is used as follows to decide if
RLOSMDIS = 0 for auto data squelch
RLOSMDIS = 1 for no data squelch
The digital block asserts RLOS when no valid pulses (per the analog section
Mindspeed Technologies
RLOS Cleared
RLOS Declared
RLOS Cleared
RLOS Declared
Test Mode
Action
(mV)
Min
—
18
—
—
—
™
Table
2-3).
Typical
(mV)
55
20
92
58
—
2.0 Functional Description
(mV)
2.3 Receiver
Max
125
—
—
—
—
2-11