lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 8

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Figure 4. 24Mbit FIFO Depth Expansion: Two Cascaded Devices
Cascading Devices for Depth Expansion
Multiple devices can be cascaded to deepen the address space. The usable 24bit address space is simply
extended for every additional device that is cascaded.
Internally, the LF3312 has a 24bit address space. When cascading LF3312s, each device’s write and read
pointers behave identically. The LF3312 was designed to be cascaded in parallel. That is, the inputs of each
device are tied together. The input data word (the data word placed on the AIN input port) is to be common
for all devices. Similarly, the outputs of all devices are tied together. Only one device drives the shared
output bus at one time, controlled automatically through internal bus enables.
Each device in a cascade of N devices is responsible for 1/N of the address space. That is, each device
writes and/or reads based on the common W/R pointer locations and where that particular device sits in
the cascade. Configuration Register C[3:0] (BASE_ADDR) is used to define each device’s place in the
cascade.
When cascading LF3312s, only singe-channel modes are supported (OPMODES 0 to 3). All write enables
AWEN/BWEN and AIEN/BIEN must be tied together, as must read enables AREN/BREN (see the device
connection diagram below).
The configuration registers of each device must be programmed identically, depending on mode/function,
except for Register C. Register C defines which region of the 24bit address space the particular device is
responsible for. Within Register C, there is a 4bit BASE_ADDR and 4bit CASCADE word. BASE_ADDR
determines the region of address space each device controls, and CASCADE defines how many devices
are in cascade. Register C effectively is programmed as “Chip n of N”.
ADDR
WCLK
ACLR
BCLR
ASET
BSET
AIN
WEN
IEN
11-0
11-0
12
12
8
AWCLK
BWCLK
ASET
BSET
ACLR
BCLR
AWEN
BWEN
AIEN
BIEN
AIN
BIN
AWCLK
BWCLK
ASET
BSET
ACLR
BCLR
AWEN
BWEN
AIEN
BIEN
AIN
BIN
LF3312_1
LF3312_2
AREN
BREN
RCLR
AOUT
BOUT
AREN
BREN
RCLR
RCLK
RSET
RCLK
RSET
AOUT
BOUT
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
12
12
Video Imaging Product
ADDR
AOUT
RCLK
REN
RSET
RCLR
23-12
11-0
August 8, 2006 LDS.3312 O
LF3312