lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 28

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Write Reset Timing
Read Reset Timing
Random Access Read Pointer ‘Jump’ Timing
Q[11:0]
WEN = LOW
CLR and SET both programmed to be falling edge sensitive
*
*
D[11:0]
Rising Edge 4: Sets Write Pointer to Address A (based on WADDR) and latches data on D to be written in Address A
RCLK
Rising Edge 1: Clears Write Pointer and latches data on D to be written in address 0
WCLK
WCLR
WSET
CLR
REN = LOW
NOTE: CLR programmed as being falling edge sensitive
It takes 9 REN-enabled rising edges of RCLK (including the edge that latches a LOW on CLR) to pass the contents of address 0 to the Q port.
ADDR
Q[11:0]
RCLK
RSET
23-0
OE = LOW
NOTE: RSET programmed to be falling edge sensitive
NOTE: It takes 14 rising edges of RCLK upon setting/jumping the Read pointer
(to the 24bit Address "A" on ADDR) for the contents of location A to be dumped onto Q
(n)
t
D
REN = LOW WADDRSEL= LOW RADDRSEL= HIGH OPMODE[2:0]=001 MARK_SEL (Register 9[3]) =1
t
RWS
(n–2)
(n)
(n+1)
1
t
RWH
(n-1)
t
RWS
(n+1)
t
t
DS
DS
A
23–0
(0)
2
t
1
1
DH
t
DH
(n)
(n+2)
(1)
2
....
28
13
(2)
3
8
t
RWH
(n+13)
t
RWS
14
(n+8)
(A)
t
D
12-Mbit Frame Buffer / FIFO
4
9
t
D
(A)
Preliminary Datasheet
(A+1)
(0)
Video Imaging Product
10
5
(A+1)
August 8, 2006 LDS.3312 O
(1)
LF3312