lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 21

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Configuration Register Definitions
Register 9[7:6] = TRS_SYNC[1:0] - response to embedded TRS EAV (a)
00
01
10
11
Register 9[5] = B_FLD frame/field sync select, chnl B
0
1
Register 9[4] = A_FLD frame/field sync select, chnl A
0
1
Register 9[3] MARK_SEL - This signal is used in combination with pin BCLR to determine to
effect of bringing RSET low on the read pointer(s). When RSET goes to 0:
0
1
OPMODE BCLR
0-3
0-3
4-7
force read pointer(s) to marked address(es) (dflt)
force read pointer(s) as shown in following table:
disable TRS sync detection (dflt)
F-bit of embedded TRS EAV marks current write pointer.
F-bit of embedded TRS EAV sets current write pointer to value
set by BOUT/BIN or ALAT (1-chnl.modes) or ALAT & BLAT (2-chnl.
modes, respectively).
F-bit of embedded TRS EAV clears current write pointer.
use only falling F-bit in EAV; ignore rising (dflt)
use both rising and falling F-bit in EAV
use only falling F-bit in EAV; ignore rising (dflt)
use both rising and falling F-bit in EAV
- If B_FLD = 0 (frame-based sync), action is on each B-channel
EAV with F = 0 for which the preceding EAV had F = 1.
- If B_FLD = 1 (field-based sync), action is on each B-chan EAV
whose F differs from that of the preceding EAV. A_FLD affects
the tA-channel operation in the same fashion.
1
0
x
21
Read Pointer Equals:
BIN/BOUT address
BLAT address
Ch. A=ALAT, Ch. B=BLAT
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312