lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 7

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Operating Modes
Random Access mode (OPMODE = 1)
Random Access mode is a single-channel FIFO mode, with the capability of either full-time write or read
pointer Random Accessability. This mode also supports write and read pointer jumps to arbitrary locations
throughout the address space. Unlike Asynchronous Single-Channel FIFO mode (OPMODE=3), Random
Access mode does not disable memory reads when the read pointer catches up to the write pointer.
Write pointer manipulation can be done through setting (jumping) the write pointer to the 24bit address
via the BIN and BOUT ports or to the ALATENCY configuration register. Read pointer manipulation can
be done through setting (jumping) the write pointer to the 24bit address via the BIN and BOUT ports or
to the BLATENCY configuration register. Periodic write and read pointer jumping can be accomplished by
supplying an address through either the BOUT/BIN address or the A or BLATENCY registers. Continuous
random access can only be accomplished through the use of the BOUT/BIN ports. When the write/read
pointers are not being set to an address, they increment sequentially.
In OPMODE 1, when BSET = 1 and BCLR = 0 the write pointer is set to the address supplied by
the BOUT/BIN ports when ASET is brought LOW. AWCLK and BWCLK must be tied together as must
AWEN and BWEN. In other words, on each active write clock cycle (rising edge of AWCLK for which
AWEN was LOW two rising edges of AWCLK previously), the user directs the write pointer to any
desired memory location, using what are otherwise the second channel data input and output ports. In
this application, BOUT[11:0] denotes the vertical (row) component, and BIN[11:0], the horizontal
(column) component, of a Cartesian set. Setting the control register ROW_LENGTH to the frame’s line
(row) length internally defines the Cartesian coordinates. Or, if desired, the concatenation of BOUT[11:0] in
front of BIN[11:0] represents a single 24-bit linear address. The user governs the mapping of (BOUT,BIN)
to the internal memory space by setting the parameter ROW_LENGTH such that ADDRESS = BOUT *
ROW_LENGTH + BIN. A ROW_LENGTH setting of 0 is interpreted as 4096, such that ADDRESS = a
24-bit concatenation of {BOUT,BIN} for this particular value. For a standard D1 video application with 1716
samples per line, the user would set ROW_LENGTH to 1716 decimal = 6B4 hex. Offset circuitry within the
LF3312 permits the user to cascade several chips in parallel and to use them collectively as a single large
memory with a seamless address space. Data are read out sequentially by rising edges of RCLK, under
the control of AREN (read enable), RSET (read pointer force to constant), and RCLR (read pointer clear to
0). Holding ASET LOW keeps the device continuously in random access write mode. Releasing ASET to its
HIGH state causes the chip to continue to write sequentially from the last-loaded address.
In OPMODE 1, when BCLR = 1, BSET = 0, MARK_SEL = 1, the read pointer is set to the address
supplied by the BOUT/BIN ports when RSET is brought LOW. AWCLK and BWCLK must be tied together
as well as AREN and BREN. As mentioned above, BOUT[11:0] represents the upper bits or the vertical
(row) address, whereas BIN[11:0] represents the lower bits or the horizontal (column) address. Releasing
RSET HIGH causes the read address pointer to increment from its last assigned location to the next
sequential address.
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12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312