lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 30

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lf3312

Manufacturer Part Number
lf3312
Description
12-mbit Frame Buffer / Fifo
Manufacturer
LOGIC Devices Incorporated
Datasheet
DEVICES INCORPORATED
LOGIC Devices Incorporated
1. Maximum Ratings indicate stress specifications only. Functional operation of these products
at values beyond those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designedto protect the chip
from damaging substrate injection currents and accumulations of static charge. Nevertheless,
conventional precautions should be observed during storage, handling, and use of these circuits
in order to avoid exposure to excessive electrical stress values.
3. This device provides hard clamping of transient undershoot. Input levels below ground will be
clamped beginning at –0.6V. The device can withstand operation with inputs or outputs in the
range of –0.5 V to +5.5 V. Device operation will not be adversely affected, however, input current
levels may be in excess of 100 mA.
4. Actual test conditions may vary from those designated but operation is guaranteed as speci-
fied.
5. I/O Ring supply current for a given application can be approximated by:
where
6. Tested in single-channel mode with 14 output pins driving 10pF loads, while toggling at an aver-
age of 30% of the 74MHz clock rate. The 10pF load is estimate of trace and downstream pin
capacitance.
7. Operating condition assumed to be most demanding reading/writing memory scenario .
8. These parameters are guaranteed but not 100% tested.
9. AC specifications are tested with input transition times less than 3 ns, output reference levels
of 1.5 V (except t dis test), and input levels of nominally 0 to 3.0V. Output loading may be a
resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and
VOL max respectively. Alternatively, a diode bridge with upper and lower current sources of IOH
and IOL respectively, and a balancing voltage of 1.5 V may be used. Parasitic capacitance is 30
pF minimum, and may be distributed.
This device has high-speed outputs capable of large instantaneous current change pulses and
fast turn-on/turn-off times. As a result, care must be exercised in the testing of this device. The
following measures are recommended:
a. A 0.1 µF ceramic capacitor should be installed between VCC and Ground leads as close to
the device as possible. Similar capacitors should be installed between device VCC and the tester
common, and device ground and tester common.
b. Ground and VCC supply planes must be brought directly to the device leads.
Notes
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
NCV F
2
2
30
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312

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