lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 2

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
LF3312 Functional Block Diagram
A/B WCLK
A/B MARK
A/B WEN
A/B CLR
A/B SET
A/B IEN
ADDR
DATA
AIN
BIN
WE
CE
RE
(x8,x10, x12)
LF3312 Overview
The LF3312 is a 12,441,600-bit memory device which can be configured by the user into either a two-
data-port single-channel or a four-data-port dual-channel architecture. The input data ports may be clocked
simultaneously or asynchronously with one another and with the output ports. Using the four 12-bit data
ports provided, the user can operate the chip as one or two 8, 10, or 12-bit channels or as a single 16, 20, or
24-bit channel, without wasting any memory resources. Since reads are non-destructive, a given data value,
once written into the memory core, may be read as many times as desired. A user requiring more storage
can cascade up to sixteen LF3312s into a larger array.
A great deal of memory addressing flexibility is offered with the LF3312. In addition to simple clearing of the
Write and Read pointers, either pointer may be set/jumped to any location within the entire address space.
Real-time random-access Writing or Reading is also supported through an external address port.
The device is controlled by sixteen instruction words of eight bits each, which may be programmed or
verified via a standard I
The 3-bit OPMODE control selects one of the chip’s operating modes, each of which has versatile submode
options:
- One-Channel FIFO With Asynchronous I/O
- Two-Channel FIFO; Both Channels Sychronized to External Signals
- One-Channel Synchronous Shift Register (Single Clock; User-set Latency)
- Two-Channel Synchronous Shift Register (Single Clock; User-set Latencies)
- One-Channel Framestore With Random Access
- Two-Channel FIFO; Channel A Synchronized to Channel B
- Two-Channel FIFO; Channel B Synchronized to Channel A
6
8
CONTROL
INTERFACE
PORTS
PARALLEL
INPUT
DATA
INPUT
PROGRAM
2
C 2-wire serial or parallel microprocessor interface.
POINTER
WRITE
LOAD
RANDOM ACCESS
ADDRESSING
MEMORY
TWO-WIRE SERIAL
2
12Mbit
INTERFACE
SDA
POINTER
READ
SCL
CONTROL
12-Mbit Frame Buffer / FIFO
OUTPUT
OUTPUT
PORTS
FLAGS
DATA
JTAG
Preliminary Datasheet
Video Imaging Product
(x8,x10, x12)
August 8, 2006 LDS.3312 O
A/B PE
A/B COLLIDE
A/B PF
RCLK
A/B REN
RSET
RCLR
TMS
TRST
TDI
TDO
TCLK
AOUT
BOUT
LF3312