lf3321qc9 LOGIC Devices Incorporated, lf3321qc9 Datasheet
lf3321qc9
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lf3321qc9 Summary of contents
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... Decimation 16:1 is supported. The LF3321 contains enough on-board memory to store 256 coefficient sets. Two separate LF Interfaces allow all 256 coefficient sets to be updated within vertical blanking. LOGIC Devices Incorporated TM CLK tPWL ...
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... CAA 7-0 CENA 12 CFA 11-0 PAUSEA LDA CLK LOGIC Devices Incorporated Parameter Cycle Time Clock Pulse Width Low Clock Pulse Width High Input Setup Time Input Hold Time Setup Time Control Inputs Hold Time Control Inputs Setup Time Coefficient Control Inputs Hold Time Coefficient Control Inputs ...
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... DEVICES INCORPORATED DESCRIPTION Figure 3. LF3321 Functional Block Diagram DATA REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1- DATA 1-16 REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 LOGIC Devices Incorporated 11-0 OUT RSLB CENA 3 LF3321 Horizontal Digital Image Filter Improved Performance LDB PAUSEB CFB 11-0 LDA PAUSEA 11-0 CFA Video Imaging Products Feb 5, 2003 LDS.3321-A ...
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... I/D Register in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse data path. Bit 5 in Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for an even or odd number of taps. LOGIC Devices Incorporated ...
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... Data reversal circuitry is placed after the multiplexers which route data from the forward data path to the reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to be properly aligned at the inputs of the ALUs. Figure 6. Data Reversal LOGIC Devices Incorporated ...
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... N, TXFRA/TXFRB should go LOW once every N clock cycles. When data reversal is disabled, the circuitry functions like an I/D Register. When feeding interleaved data through the filter, data reversal should be disabled. Bit 6 of Configuration Register 1 and Configuration Register 3 enables or disables data reversal for Filters A and B respectively. Figure 7 .Filter A and Filter B Round/Limit/Select Circuitry LOGIC Devices Incorporated RSLB DATA IN 3-0 4 ...
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... LF3321 can facilitate this by scaling the Filter B output by 2-12 before adding it to the Filter A output. Bit 3 in Configuration Register 5 determines if the Filter B output is scaled before being added to the Filter A output. Figure 8. Multiple LF3321 Cascaded Together 12 REGISTERS DIN FILTER LOGIC Devices Incorporated LF3320 LF3320 RIN ROUT I/D I/D I/D ...
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... The coefficient banks store the coefficients which feed into the multipliers in Filters A and B. There is a Banks separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using an LF Interface is discussed in the LF Interface LOGIC Devices Incorporated section. TM section. TM section ...
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... LF Interface Table 2. Configuration register 0 - Address 200H BITS 11-3 Table 3. Configuration Register 1 - Address 201H BITS 0 4 11-7 LOGIC Devices Incorporated section. TM FUNCTION ALU Mode Pass A Pass B Reserved FUNCTION Filter B Odd-Tap Interleave Mode Filter B I/D Register Length Filter B Tap Number Filter B Data Reversal Reserved ...
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... BITS 0 4 11-7 Table 6. Configuration Register 4 - Adress 204H BITS 0 1 11-2 LOGIC Devices Incorporated FUNCTION DESCRIPTION ALU Mode Filter – A Pass A Filter ALU Input A ALU Input A=Forward Register Path Pass B Filter ALU Input A ALU Input A=Reverse Register Path Reserved Must be set to “ ...
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... REGISTER ADDRESS (HEX Table 12 Fltr. B Round Regs REGISTER ADDRESS (HEX LOGIC Devices Incorporated FUNCTION DESCRIPTION Vertical Limit Enable 0 : Vertical Limiting Disabled 1 : Vertical Limiting Enabled Horizontal Limit Enable 0 : Horizontal Limiting Disabled 1 : Horizontal Limiting Enabled Reserved Must be set to “0” ...
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... W2: Select Register loaded with new data on this rising clock edge. W3: Round Register loaded with new data on this rising clock edge. W4: Limit Register loaded with new data on this rising clock edge. LOGIC Devices Incorporated affecting the data used for Filter A is held until TM ...
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... W2: Select Register loaded with new data on this rising clock edge. Figure 13. Round Register Loading Sequence with PAUSE Implementation CLK PAUSEA/PAUSEB LDA/LDB CFA/CFB 11-0 W1: Round Register loaded with new data on this rising clock edge. LOGIC Devices Incorporated COEFFICIENT SET 1 ADDR COEF COEF ...
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... Configuration or Control register at the same time, the Filter B LF Interface Filter A LF Interface register at the same time that the Filter B LF Interface Filter B LF Interface be allowed to load the configuration register. However, the Filter A LF Interface as if the write occurred. LOGIC Devices Incorporated LIMIT REGISTER ADDR DATA DATA 1 ...
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... Word - Data 5th Word - Data R = Reserved. Must be set to “0“. * This bit represents the MSB of the Lower Limit. ** This bit represents the MSB of the Upper Limit. LOGIC Devices Incorporated CFA/B11 CFA/B10 CFA/B 9 CFA/B 8 CFA/B 7 CFA/B 6 CFA/B 5 CFA/B 4 CFA/B 3 CFA/B 2 CFA/B 1 CFA ...
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... DIN11-0 can be the data input for Filter B. Conversely, when configured for a [16x16][16x1] matrix-vector operation, the coefficient banks will require 16 coefficient sets to be loaded into the coefficient memory banks; each coefficient set will have 16, 12-bit coefficients. The input data, [16x1] column-vector, will be loaded through DIN11-0. LOGIC Devices Incorporated Horizontal Digital Image Filter 12 ROUT ...
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... For the [8x8][8x1] matrix-vector configuration (dual filter mode), the first result will appear 19 clock cycles from the first data input, DIN15-0 (Filter A) and RIN15-0 (Filter B); device latency for the first result is 10 clock cycles (10+9 = 19). LOGIC Devices Incorporated Horizontal Digital Image Filter N ...
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... The LF3321 must be configured for single filter mode only, for a maximum (8x8) matrix. The user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (see Table 7). LOGIC Devices Incorporated C = COEFFICIENTS D = DATA INPUT ...
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... In addition, the user must disable the cascaded filter mode, the accumulator access mode, and the data reversal (Table 7). For additional considerations, refer to the corresponding mode of operation section. LOGIC Devices Incorporated 1 Data Set with 16 Coefficient Sets 12 ...
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... As previously stated, this mode of operation is only valid with the dual filter mode configuration. All modes of operation, that are valid in the dual filter mode, are valid with the accumulator access mode. For additional considerations, refer to the corresponding mode of operation section. Figure 22. Accumulator Access Mode LOGIC Devices Incorporated 12 I/D DIN ...
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... CAB7-0 — Coefficient Address B CAB7-0 determines which row of data in coefficient banks 8 through 15 is fed to the multipliers. CAB7-0 is latched into Coefficient Address Register B on the rising edge of CLK when CENB is LOW. Figure 23. Input Formats Figure 24. Accumulator Output Formats LOGIC Devices Incorporated Input Data – ...
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... When LDB is HIGH, data is not loaded into the Filter B LF Interface data input, a HIGH to LOW transition of LDB is required in order for the input circuitry to function properly. Therefore, LDB must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF Interface LOGIC Devices Incorporated S15 S14 S13 · ...
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... Input (RIN11-0), Cascade Output (COUT11-0), Reverse Cascade Output (ROUT11-0) and Filter B I/D Registers important to note that in Single Filter Mode, both SHENA and SHENB should be connected together. Both must be active to enable data loading in Single Filter Mode. SHENA is latched on the rising edge of CLK. LOGIC Devices Incorporated Horizontal Digital Image Filter Improved Performance 23 ...
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... PAUSEB — LF Interface When PAUSEB is HIGH, the Filter B LF Interface a LOW state. This effectively allows the user to load coefficients and control registers at a slower rate than the master clock (see the LF Interface LOGIC Devices Incorporated Pause TM loading sequence is halted until PAUSEA is returned to TM section for a full discussion) ...
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... OED & OEC) OED OEC DOUT 15-0 ROUT COUT 11-0/ 11-0 LOGIC Devices Incorporated Above which useful life may be impaired (Notes 1,2,3,8) To meet specified electrical and switching characteristics Temperature Range (Ambient) 0°C to +70°C -55°C to +125°C Over Operating Conditions (Note 4) Parameter Test Condition V = Min ...
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... Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. LOGIC Devices Incorporated N = total number of device outputs capacitive load per output ...
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... V for Z-to-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. Figure A. Output Loading Circuit DUT C L LOGIC Devices Incorporated test, the transition is measured to the 1.5V crossing point with datasheet loads. For ...
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... CFA 33 3 CFA 34 2 CFA 35 1 CFA 36 0 Plastic Quad Flatpack (Q5) 0°C to 70°C--Commercial Screening Speed 9 ns LF3321QC9 LOGIC Devices Incorporated Horizontal Digital Image Filter Improved Performance Top View 144-pin 28 LF3321 108 GND 107 COUT 11 106 COUT 10 105 ...