lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 6

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Operating Modes
Single-channel synchronous shift register mode (OPMODE = 0)
In OPMODE 0, the LF3312 becomes a single channel shift register with programmable total latency up to
2
In OPMODE 0, the user provides a single clock for both the input and output clocks and specifies a desired
input-to-output data path latency, (ALAT) via the control interface. AWCLK, BWCLK, and RCLK must be tied
together, as should AWEN, BWEN, AREN, and BREN. When activated, ALAT will begin to countdown, and
once expired, will allow the inputs to begin to appear on the outputs. In OPMODE 0, ALAT countdown can
be activated in two ways. The first occurs when the first enable is brought LOW after the LOAD signal has
been set HIGH after MPU programming. The second is by bringing LOAD HIGH once MPU programming
complete, after the enables have been brought LOW.
Dual-channel synchronous shift register mode (OPMODE = 4)
The operation of dual-channel shift register mode is identical to single-channel operation, with the addition
of a second independent channel. The latency for each channel is independent and set by the user.
The user must also supply a single clock to tie AWCLK, BWCLK, and RCLK together, and must load the
respective desired constant latency for each channel, (ALAT, BLAT), via the microprocessor bus. ALAT
and BLAT are activated in the same manner as in OPMODE 0, with the respective inputs being made
available on the outputs once ALAT or BLAT expire. In this mode, AWEN and AREN must be tied together,
as must be BWEN and BREN.
Dual-channel master/slave mode (OPMODE = 5)
OPMODE 5 is one of two master/slave synchronizing modes where two data streams are written into the
LF3312 at independent rates and with independent TRS timing information. In this mode, both channels
are synchronized together based on the sync data supplied to channel A or by the embedded TRS data
within the A channel.
When in OPMODE 5, channel A operates as a fully synchronous master shift register, to which the data in
asynchronous FIFO channel B is re-timed. The user drives AWCLK and RCLK from the incoming AIN data
stream’s sample clock, and BWCLK from the BIN data stream’s clock. The user also specifies whether sync
timing will be derived from TRS words embedded within the incoming data streams or from signals applied
to ACLR and ASET or to AMARK and BMARK. AWEN, AREN and BREN must be tied together to maintain
constant reference latency through channel A and to synchronize the outputs. When a MARK occurs, the
signal MARK_ACTIVE_RSET when set high, allows the read pointer to be set to the current value of the
write pointer “ALAT” RCLK cycles later. If the user sets MARK_ACTIVE_RSET = 0, the LF3312 will ignore
the internal read pointer set.
Dual-channel slave/master mode (OPMODE = 6)
OPMODE 6 is the reverse of OPMODE 5, with the difference being that the two streams are synchronized to
the timing information applied to the B channel or embedded within the B channel as TRS data.
This OPMODE is identical to the previous, except that channel A is the slave FIFO and channel B is the
master shift register, and RCLK needs to be tied to BWCLK, and BWEN needs to be tied to BREN and
AREN. Similarly to mode 5, when a MARK occurs, the signal MARK_ACTIVE_RSET when set high, allows
the read pointer to be set to the registered value of the write pointer BLAT number of RCLK cycles later. If
the user sets MARK_ACTIVE_RSET = 0, the LF3312 will ignore the internal read pointer set.
24
-8 clock cycles. Writes and reads occur simultaneously, hence synchronous operation.
6
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312