mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 645
mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
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And finally the frequency relationship is defined as
With the above inputs the resistance can be calculated as:
The capacitance C
The capacitance C
The stabilization delays shown in
component selection (e.g. crystal, XFC filter).
A.5.3.2
The basic functionality of the PLL is shown in
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in
Freescale Semiconductor
f
n
C
C
R
C
s
s
=
<
=
=
20 C
------------------------------------------
f
------------ -
VCO
f
2
---------------------------- -
--------------------- -
ref
2
2
f
K
C
+
Jitter Information
p
=
n f
2
R
2
1
f
s
p
C
ref
can now be calculated as:
should be chosen in the range of:
C
+
s
0.516
-------------- -
f
synr
C
10
2
R
----- -
50
1
+
;
1
Table A-17
=
f
ref
MC9S12HZ256 Data Sheet, Rev. 2.05
C
0.9
is measured and input voltage to the VCO is adjusted
<
------------ -
4 50
f
ref
are dependant on PLL operational settings and external
Figure
;
=
A-3. With each transition of the clock f
0.9
Appendix A Electrical Characteristics
Figure
cmp
A-4.
, the
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