mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 313

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mc9s12hz256v2

Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
11.3.2.2
Read and write anytime
Freescale Semiconductor
IBC[7:0]
Reset
Field
7:0
W
R
IBC7
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in
IIC Frequency Divider Register (IBFD)
0
7
Table
11-4.
IBC5-3
(bin)
000
001
010
011
100
101
110
111
IBC6
Figure 11-3. IIC Bus Frequency Divider Register (IBFD)
= Unimplemented or Reserved
0
6
Table 11-4. I-Bus Tap and Prescale Values
scl2start
(clocks)
IBC2-0
Table 11-3. IBFD Field Descriptions
(bin)
000
001
010
011
100
101
110
111
126
14
30
62
MC9S12HZ256 Data Sheet, Rev. 2.05
IBC5
2
2
2
6
0
5
IBC4
scl2stop
SCL Tap
(clocks)
(clocks)
0
4
129
10
12
15
17
33
65
5
6
7
8
9
7
7
9
9
Description
IBC3
0
3
SDA Tap
(clocks)
(clocks)
scl2tap
126
14
30
62
1
1
2
2
3
3
4
4
4
4
6
6
Chapter 11 Inter-Integrated Circuit (IICV2)
IBC2
0
2
(clocks)
tap2tap
128
16
32
64
1
2
4
8
IBC1
0
1
IBC0
0
0
313

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