mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 130

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2
Port L is associated with the analog-to-digital converter (ATD) and the liquid crystal display (LCD) driver.
If the ATD module is enabled, the AN[15:8] inputs of ATD module are available on port L pins PL[7:0].
If the corresponding LCD frontplane drivers are enabled, the FP[31:29] and FP[19:16] outputs of LCD
module are available on port L pins PL[7:0] and the general purpose I/Os are disabled.
For the pins of port L to be used as inputs, the corresponding LCD frontplane drivers must be disabled and
the associated ATDDIEN0 register in the ATD module must be set to 1 (digital input buffer is enabled).
The ATDDIEN0 register does not affect the port L pins when they are configured as outputs.
Refer to the LCD block description chapter for information on enabling and disabling the LCD and its
frontplane drivers. Refer to the ATD block description chapter for information on the ATDDIEN0 register.
During reset, port L pins are configured as inputs with pull down.
4.3.2.1
Read: Anytime. Write: Anytime.
If the data direction bit of the associated I/O pin (DDRLx) is set to 1 (output), a write to the corresponding
I/O Register bit sets the value to be driven to the Port L pin. If the data direction bit of the associated I/O
pin (DDRLx) is set to 0 (input), a write to the corresponding I/O Register bit takes place but has no effect
on the Port L pin.
If the associated data direction bit (DDRLx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRLx) is set to 0 (input) and the associated ATDDIEN0 bits is set to
0 (digital input buffer is disabled), the associated I/O register bit (PTLx) reads “1”.
If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1
(digital input buffer is enabled), and the LCD frontplane driver is enabled (and LCD module is enabled),
the associated I/O register bit (PTLx) reads “1”.
If the associated data direction bit (DDRLx) is set to 0 (input), the associated ATDDIEN0 bit is set to 1
(digital input buffer is enabled), and the LCD frontplane driver is disabled (or LCD module is disabled),
a read returns the value of the pin.
130
Reset
LCD:
ATD:
W
R
Port L
AN15
PTL7
Port L I/O Register (PTL)
1
0
7
AN14
PTL6
1
0
6
Figure 4-10. Port L I/O Register (PTL)
AN13
PTL5
MC9S12HZ256 Data Sheet, Rev. 2.05
1
0
5
AN12
PTL4
1
0
4
AN11
PTL3
1
0
3
PTL2
AN10
1
0
2
Freescale Semiconductor
PTL1
AN9
1
0
1
PTL0
AN8
1
0
0