mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 190

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Clocks and Reset Generator (CRGV4)
running at minimum operating frequency; this mode of operation is called self-clock mode. This requires
CME = 1 and SCME = 1. If the MCU was clocked by the PLL clock prior to entering self-clock mode, the
PLLSEL bit will be cleared. If the external clock signal has stabilized again, the CRG will automatically
select OSCCLK to be the system clock and return to normal mode. See
Checker” for more information on entering and leaving self-clock mode.
5.4.8
The RTI can be stopped by setting the associated rate select bits to 0.
The COP can be stopped by setting the associated rate select bits to 0.
5.4.9
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual wait mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during wait mode.
Table 5-10
After executing the WAI instruction the core requests the CRG to switch MCU into wait mode. The CRG
then checks whether the PLLWAI, CWAI and SYSWAI bits are asserted (see
the configuration the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit,
disables the PLL, disables the core clocks and finally disables the remaining system clocks. As soon as all
clocks are switched off wait mode is active.
190
lists the individual configuration bits and the parts of the MCU that are affected in wait mode.
Low-Power Operation in Run Mode
Low-Power Operation in Wait Mode
1
In order to detect a potential clock loss, the CME bit should be always
enabled (CME=1).
If CME bit is disabled and the MCU is configured to run on PLL clock
(PLLCLK), a loss of external clock (OSCCLK) will not be detected and will
cause the system clock to drift towards the VCO’s minimum frequency
f
ramps up to its PLL target frequency. If the MCU is running on external
clock any loss of clock will cause the system to go static.
SCM
Oscillator
Refer to oscillator block description for availability of a reduced oscillator amplitude.
System
Core
COP
PLL
RTI
. As soon as the external clock is available again the system clock
Table 5-10. MCU Configuration During Wait Mode
PLLWAI
stopped
—
—
—
—
—
MC9S12HZ256 Data Sheet, Rev. 2.05
stopped
CWAI
—
—
—
—
—
NOTE
SYSWAI
stopped
stopped
—
—
—
—
stopped
RTIWAI
—
—
—
—
—
COPWAI
stopped
Section 5.4.4, “Clock Quality
—
—
—
—
—
Figure
ROAWAI
reduced
5-23). Depending on
Freescale Semiconductor
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—
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1