mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 347

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mc9s12hz256v2

Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
2
12.3.2.7
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
Read: Anytime
Write: Anytime for TXEx flags when not in initialization mode; write of 1 clears flag, write of 0 is ignored
Freescale Semiconductor
WUPIE and WUPE (see
mechanism from stop or wait is required.
Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the
only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see
Flag Register
OVRIE
RXFIE
Field
1
0
Reset:
W
R
Overrun Interrupt Enable
0 No interrupt request is generated from this event.
1 An overrun event causes an error interrupt request.
Receiver Full Interrupt Enable
0 No interrupt request is generated from this event.
1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
MSCAN Transmitter Flag Register (CANTFLG)
(CANRFLG)”).
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
7
Table 12-12. CANRIER Register Field Descriptions (continued)
Section 12.3.2.1, “MSCAN Control Register 0
Figure 12-8. MSCAN Transmitter Flag Register (CANTFLG)
= Unimplemented
6
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
NOTE
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
4
0
0
Description
(CANCTL0)”) must both be enabled if the recovery
0
0
3
TXE2
Section 12.3.2.5, “MSCAN Receiver
2
1
TXE1
1
1
TXE0
0
1
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