mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 412
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
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Chapter 13 Serial Communication Interface (SCIV4)
Figure 13-20
after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error flag.
In
noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.
13.4.5.4
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it
sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag
because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
412
RT CLOCK COUNT
RT CLOCK COUNT
RESET RT CLOCK
RESET RT CLOCK
Figure
RT CLOCK
RT CLOCK
SAMPLES
SAMPLES
13-21, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the
RXD
RXD
shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample
Framing Errors
1
1
1
1
1
1
1
1
1
1
Figure 13-20. Start Bit Search Example 5
Figure 13-21. Start Bit Search Example 6
1
1
MC9S12HZ256 Data Sheet, Rev. 2.05
1
1
1
1
1
1
0
0
0
0
1
0
START BIT
START BIT
1
0
0
1
NO START BIT FOUND
0
0
0
1
0
0
0
Freescale Semiconductor
0
0
LSB
LSB
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