mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 92

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Resets, Interrupts, and General System Control
5.6.3
The LVD system has a low-voltage warning flag to indicate to the user that the supply voltage is
approaching the low-voltage condition. When a low-voltage warning condition is detected and is
configured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt
request will occur.
5.7
The PTA0 pin is shared with the MCLK clock output. If the MCSEL bits are all zeroes, the MCLK clock
is disabled. Setting any of the MCSEL bits causes the PTA0 pin to output a divided version of the internal
MCU bus clock regardless of the state of the port data direction control bit for the pin. The divide ratio is
determined by the MCSEL bits. The slew rate and drive strength for the pin are controlled by PTASE0 and
PTADS0, respectively.
5.8
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of
5.8.1
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
92
Reset
W
R
Table 4-2
MCLK Output
Reset, Interrupt, and System Control Registers and Control Bits
Low-Voltage Warning (LVW) Interrupt Operation
Interrupt Pin Request Status and Control Register (IRQSC)
0
0
7
and
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
= Unimplemented or Reserved
Operation.”
IRQPDD
Table 4-3
0
6
in
MC9S08DZ128 Series Data Sheet, Rev. 1
IRQEDG
Chapter 4,
0
5
“Memory,” of this data sheet for the absolute address
IRQPE
0
4
IRQF
3
0
IRQACK
0
0
2
Freescale Semiconductor
IRQIE
0
1
IRQMOD
0
0