mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 179

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

The nine states of the MCG are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
8.4.1.1
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
In FLL engaged internal mode, the MCGOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL clock frequency locks to a multiplication factor, as selected by the
DRS and DMX32 bits, times the internal reference frequency. The MCGLCLK is derived from the FLL
and the PLL is disabled in a low power state.
8.4.1.2
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FLL engaged external mode, the MCGOUT clock is derived from the FLL clock which is controlled by
the external reference clock. The external reference clock which is enabled can be an external
crystal/resonator or it can be another external clock source.The FLL clock frequency locks to a
multiplication factor, as selected by the DRS and DMX32 bits, times the external reference frequency, as
selected by the RDIV, RANGE and DIV32 bits. The MCGLCLK is derived from the FLL and the PLL is
disabled in a low power state.
8.4.1.3
In FLL bypassed internal (FBI) mode, the MCGOUT clock is derived from the internal reference clock
and the FLL is operational but its output clock is not used. This mode is useful to allow the FLL to acquire
its target frequency while the MCGOUT clock is driven from the internal reference clock.
The FLL bypassed internal mode is entered when all the following conditions occur:
In FLL bypassed internal mode, the MCGOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL clock frequency locks to a multiplication
Freescale Semiconductor
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CLKS bits are written to 00
IREFS bit is written to 1
PLLS bit is written to 0
CLKS bits are written to 00
IREFS bit is written to 0
PLLS bit is written to 0
RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
CLKS bits are written to 01
IREFS bit is written to 1
PLLS bit is written to 0
LP bit is written to 0
FLL Engaged Internal (FEI)
FLL Engaged External (FEE)
FLL Bypassed Internal (FBI)
MC9S08DZ128 Series Data Sheet, Rev. 1
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
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