mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 139

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mc9s08dz32amlfr

Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
6.5.11
Port L is controlled by the registers listed below.
6.5.11.1
6.5.11.2
Freescale Semiconductor
PTLDD[7:0]
PTLD[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
W
W
R
R
PTLDD7
PTLD7
Port L Registers
Port L Data Register Bits — For port L pins that are inputs, reads return the logic level on the pin. For port L
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port L pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTLD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.
Data Direction for Port L Bits — These read/write bits control the direction of port L pins and what is read for
PTLD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port L bit n and PTLD reads return the contents of PTLDn.
Port L Data Register (PTLD)
0
Port L Data Direction Register (PTLDD)
0
7
7
PTLDD6
PTLD6
0
0
6
6
Figure 6-66. Port L Data Direction Register (PTLDD)
Table 6-64. PTLDD Register Field Descriptions
Table 6-63. PTLD Register Field Descriptions
Figure 6-65. Port L Data Register (PTLD)
MC9S08DZ128 Series Data Sheet, Rev. 1
PTLDD5
PTLD5
0
0
5
5
PTLDD4
PTLD4
0
0
4
4
Description
Description
PTLDD3
PTLD3
3
0
3
0
PTLDD2
PTLD2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTLDD1
PTLD1
0
0
1
1
PTLDD0
PTLD0
0
0
0
0
139

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