mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 181

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.4.1.6
In PLL bypassed external (PBE) mode, the MCGOUT clock is derived from the external reference clock
and the PLL is operational but its output clock is not used. This mode is useful to allow the PLL to acquire
its target frequency while the MCGOUT clock is driven from the external reference clock.
The PLL bypassed external mode is entered when all the following conditions occur:
In PLL bypassed external mode, the MCGOUT clock is derived from the external reference clock. The
external reference clock which is enabled can be an external crystal/resonator or it can be another external
clock source. The PLL clock frequency locks to a multiplication factor, as selected by the VDIV bits, times
the external reference frequency, as selected by the RDIV, RANGE and DIV32 bits. If BDM is enabled
then the MCGLCLK is derived from the DCO (open-loop mode) divided by two. If BDM is not enabled
then the FLL is disabled in a low power state.
In this mode, the DRST bit reads 0 regardless of whether the DRS bit is set to 1 or 0.
8.4.1.7
The bypassed low power internal (BLPI) mode is entered when all the following conditions occur:
In bypassed low power internal mode, the MCGOUT clock is derived from the internal reference clock.
The PLL and the FLL are disabled at all times in BLPI mode and the MCGLCLK will not be available for
BDC communications If the BDM becomes active the mode will switch to FLL bypassed internal (FBI)
mode.
In this mode, the DRST bit reads 0 regardless of whether the DRS bit is set to 1 or 0.
8.4.1.8
The bypassed low power external (BLPE) mode is entered when all the following conditions occur:
Freescale Semiconductor
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CLKS bits are written to 10
IREFS bit is written to 0
PLLS bit is written to 1
RDIV bits are written to divide reference clock to be within the range of 1 MHz to 2 MHz
LP bit is written to 0
CLKS bits are written to 01
IREFS bit is written to 1
PLLS bit is written to 0
LP bit is written to 1
BDM mode is not active
CLKS bits are written to 10
IREFS bit is written to 0
PLLS bit is written to 0 or 1
LP bit is written to 1
PLL Bypassed External (PBE)
Bypassed Low Power Internal (BLPI)
Bypassed Low Power External (BLPE)
MC9S08DZ128 Series Data Sheet, Rev. 1
Chapter 8 Multi-Purpose Clock Generator (S08MCGV2)
181