mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 127

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mc9s08dz32amlfr

Manufacturer Part Number
mc9s08dz32amlfr
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
6.5.7.3
6.5.7.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
Freescale Semiconductor
PTGPE[7:0]
PTGSE[7:0]
Reset:
Reset:
Field
Field
7:0
7:0
rate control to the desired value to ensure correct operation.
W
W
R
R
PTGPE7
PTGSE7
Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
Port G Pull Enable Register (PTGPE)
0
Port G Slew Rate Enable Register (PTGSE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
PTGPE6
PTGSE6
Figure 6-44. Internal Pull Enable for Port G Register (PTGPE)
Figure 6-45. Slew Rate Enable for Port G Register (PTGSE)
0
0
6
6
Table 6-42. PTGPE Register Field Descriptions
Table 6-43. PTGSE Register Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
PTGPE5
PTGSE5
0
0
5
5
PTGPE4
PTGSE4
NOTE
0
0
4
4
Description
Description
PTGPE3
PTGSE3
3
0
3
0
PTGPE2
PTGSE2
Chapter 6 Parallel Input/Output Control
0
0
2
2
PTGPE1
PTGSE1
0
0
1
1
PTGPE0
PTGSE0
0
0
0
0
127

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