mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 389

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Active BDM:
17.3.1.1
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
Reset in
Freescale Semiconductor
Normal
Reset
BDMACT
BKPTEN
ENBDM
CLKSW
Field
FTS
W
7
6
5
4
3
R
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
clock source.
0 Alternate BDC clock source
1 MCU bus clock
0
1
7
BDC Status and Control Register (BDCSCR)
instruction
opcode)
= Unimplemented or Reserved
BDMACT
Figure 17-5. BDC Status and Control Register (BDCSCR)
0
1
6
Table 17-2. BDCSCR Register Field Descriptions
BKPTEN
MC9S08DZ128 Series Data Sheet, Rev. 1
0
0
5
FTS
0
0
4
Description
CLKSW
0
1
3
WS
0
0
2
Chapter 17 Development Support
WSF
1
0
0
DVF
0
0
0
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