mc9s08dz32amlfr Freescale Semiconductor, Inc, mc9s08dz32amlfr Datasheet - Page 437

• Manufacturer Part Number: mc9s08dz32amlfr
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

1
2
3
4
5
6
7
8
9
Num C
15
16
17
18
19
20
21
22
Freescale Semiconductor
This applies when TRIM register at value (0x80) and FTRIM control bit at value (0x0). These values load when in BDM modes.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit
is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a
crystal/resonator is being used as the reference, this specification assumes it is already running.
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE,
BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V
These jitter measurements are based upon a 40 MHz MCGOUT clock frequency.
In some specifications, this value is described as, “Long term accuracy of PLL output clock (averaged over 2 ms)” with symbol
“f
In some specifications, this value is described as “Jitter of PLL output clock measured over 625 ns” with symbol “f
The parameter is unchanged, but the description has been changed for clarification purposes.
Below D
already in lock, then the MCG may stay in lock.
Below D
pll_jitter_2ms
Table A-12. MCG Frequency Specifications (Temperature Range = –40 to 125°C Ambient) (continued)
D PLL reference frequency range
D Lock entry frequency tolerance
D Lock exit frequency tolerance
D Lock time - FLL
T
T
T
T
RMS frequency variation of a single clock cycle measured
2 ms after reference edge.
Maximum frequency variation averaged over 2 ms
window.
RMS frequency variation of a single clock cycle measured
625 ns after reference edge.
Maximum frequency variation averaged over 625 ns
window.
lock
unl
minimum, the MCG will not exit lock if already in lock. Above D
.” The parameter is unchanged, but the description has been changed for clarification purposes.
minimum, the MCG is guaranteed to enter lock. Above D
DD
and V
Rating
SS
6
7
and variation in crystal oscillator frequency increase the C
9
8
MC9S08DZ128 Series Data Sheet, Rev. 1
f
f
f
pll_maxjit_625ns
lock
pll_cycjit_625ns
f
pll_maxjit_2ms
pll_cycjit_2ms
Symbol
t
f
fll_lock
maximum, the MCG will not enter lock. But if the MCG is
D
pll_ref
D
lock
unl
unl
maximum, the MCG is guaranteed to exit lock.
± 1.49
± 4.47
Min
1.0
—
—
—
—
—
Appendix A Electrical Characteristics
Jitter
Typical
0.590
0.566
percentage for a given interval.
0.001
0.113
—
—
—
—
5
5
1075(1/
t
fll_acquire+
± 2.98
± 5.97
Max
2.0
—
—
—
—
pll_jitter_625ns
BUS
f
int_t)
.
Unit
MHz
%f
%f
%f
%f
437
%
%
s
pll
pll
pll
pll
.”