xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 6

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

TAP AC Parameters
Table 6
Table 6: Test Access Port Timing Parameters
Additional Features for the XQF32P
Internal Oscillator
The 32-Mbit XQF32P Platform Flash PROMs include an
optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled when programming
the PROM, and the oscillator can be set to either the default
frequency or to a slower frequency
Configuration Master with Internal Oscillator as Clock
Source," page
CLKOUT
The 32-Mbit XQF32P Platform Flash PROMs include the
programmable option to enable the CLKOUT signal which
allows the PROM to provide a source synchronous clock
aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources: the
CLK input pin or the internal oscillator. The input clock source
is selected during the PROM programming sequence.
Output data is available on the rising edge of CLKOUT.
DS541 (v1.0) November 27, 2006
Product Specification
T
T
T
T
T
T
CKMIN
MSS
MSH
DIS
DIH
DOV
Symbol
shows the timing parameters for the TAP waveforms shown in
TCK
TDO
TMS
TDI
R
30).
TCK minimum clock period when V
TMS setup time when V
TMS hold time when V
TDI setup time when V
TDI hold time when V
TDO valid delay when V
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
T
CKMIN
("XQF32P PROM as
T
DIS
T
MSS
CCJ
CCJ
CCJ
CCJ
CCJ
Figure 3: Test Access Port Timing
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
Description
CCJ
www.xilinx.com
= 2.5V or 3.3V
T
DIH
T
MSH
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. On CE
rising edge transition, if OE/RESET is High and the PROM
terminal count has not been reached, then CLKOUT
remains active for an additional eights clock cycles before
being disabled. On a OE/RESET falling edge transition,
CLKOUT is immediately disabled. When disabled, the
CLKOUT pin is put into a high-impedance state and should
be pulled High externally to provide a known state.
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and drives the CEO pin enabling the next
PROM in the PROM chain. The next PROM begins driving
the CLKOUT signal once that PROM is enabled and data is
available for transfer.
During high-speed parallel configuration without
compression, the FPGA drives the BUSY signal on the
configuration interface. When BUSY is asserted High, the
PROMs internal address counter stops incrementing, and
the current data value is held on the data outputs. While
BUSY is High, the PROM continues driving the CLKOUT
signal to the FPGA, clocking the FPGA’s configuration logic.
Figure
T
DOV
3.
Min
100
10
25
10
25
–
DS541_03_111706
Max
30
–
–
–
–
–
Units
ns
ns
ns
ns
ns
ns
6