xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 19

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

DS541 (v1.0) November 27, 2006
Product Specification
TDI
TMS
TCK
TDO
Revision
Control
Design
V
Logic
CCJ
V
CCO
V
R
Figure 12: Configuring Multiple Devices with Design Revisioning in Slave SelectMAP Mode
CCINT
Notes:
1. For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2. For compatible voltages, refer to the appropriate data sheet.
3. RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4. The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for high
5. In Slave SelectMAP mode, the configuration interface can be clocked by an external oscillator, or optionally the
6 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then must be tied to V
XQF32P
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
V
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
CCINT
CCO
CCJ
frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
CLKOUT signal can be used to drive the FPGA's configuration clock (CCLK). If the XQF32P PROM's CLKOUT signal
is used, then it must be tied to a 4.7KΩ resistor pulled up to V
a 4.7 kΩ pull-up resistor
External
Oscillator
(2)
EN_EXT_SEL
REV_SEL[1:0]
CF
DONE
PROG_B
CS_B[1:0]
(2)
OE/RESET
(5)
BUSY
CLK
D[0:7]
CF
CEO
TDO
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
CE
(5)
(6)
(4)
V
CCJ
V
CCO
V
CCINT
XQF32P
Platform Flash
PROM
First
PROM
(PROM 0)
VCCINT
V
V
TDI
TMS
TCK
EN_EXT_SEL
REV_SEL[1:0]
GND
CCO
CCJ
(2)
(2)
OE/RESET
BUSY
CLK
D[0:7]
CF
CEO
TDO
CCO
CE
(5)
(6)
(4)
www.xilinx.com
.
V
CCO
(2)
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
Xilinx FPGA
Slave SelectMAP
GND
(4)
MODE PINS
RDWR_B
CS_B
TDO
CCO
(1)
via
I/O
(3)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
Xilinx FPGA
Slave SelectMAP
GND
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
ds541_12_070906
I/O
(3)
19