xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 17

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

DS541 (v1.0) November 27, 2006
Product Specification
TMS
TDO
TCK
TDI
V
CCJ
V
CCO
Figure 10: Configuring Multiple Devices with Identical Patterns in Master/Slave SelectMAP Mode
V
CCINT
R
V
V
V
TDI
TMS
TCK
GND
Notes:
1 For Mode pin connections and DONE pin pull-up value, refer to the appropriate FPGA data sheet.
2 For compatible voltages, refer to the appropriate data sheet.
3 CS_B (or CS) and RDWR_B (or WRITE) must be either driven Low or pulled down exernally. One option is shown.
4 The BUSY pin is only available with the XQF32P Platform Flash PROM, and the connection is only required for
5 For the XQF32P the CF pin is a bidirectional pin, and if CF is not connected to PROGB, then it must be tied to V CCO via a
CCINT
CCO
CCJ
XQF32P
Platform Flash
PROM
Cascaded
PROM
(PROM 1)
high-frequency SelectMAP mode configuration. For BUSY pin requirements, refer to the appropriate FPGA data sheet.
4.7 kΩ pull-up resistor.
(2)
(2)
OE/RESET
BUSY
D[0:7]
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
CF
CEO
TDO
CLK
CE
(5)
(4)
V
CCJ
V
CCO
V
CCINT
V
V
V
TDI
TMS
TCK
GND
CCINT
CCO
CCJ
XQF32P
Platform Flash
PROM
First
PROM
(PROM 0)
(2)
(2)
OE/RESET
BUSY
D[0:7]
CF
CEO
TDO
CLK
CE
www.xilinx.com
(5)
(4)
V
CCO
(2)
(1)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Master SelectMAP
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
I/O
I/O
(3)
(3)
D[0:7]
CCLK
DONE
INIT_B
PROG_B
BUSY
TDI
TMS
TCK
GND
Xilinx FPGA
Slave SelectMAP
(4)
MODE PINS
RDWR_B
CS_B
TDO
(1)
ds541_10_080406
I/O
I/O
(3)
(3)
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