xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 2

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the
configuration.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, the PROM can be used to drive the FPGA’s
configuration clock.
The XQF32P QPro version of the Platform Flash PROM
also supports Master SelectMAP and Slave SelectMAP (or
Slave Parallel) FPGA configuration modes. When the FPGA
is in Master SelectMAP mode, the FPGA generates a
configuration clock that drives the PROM. When the FPGA
is in Slave SelectMAP Mode, either an external oscillator
generates the configuration clock that drives the PROM and
the FPGA, or optionally, the XQF32P PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
the PROM DATA (D0-D7) pins. New data is available a short
access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel /Slave SelecMAP mode.
The XQF32P QPro version of the Platform Flash PROM
provides additional advanced features. A built-in data
decompressor supports utilizing compressed PROM files,
and design revisioning allows multiple design revisions to
be stored on a single PROM or stored across several
PROMs. For design revisioning, external pins or internal
control bits are used to select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when
targeting larger FPGA devices or targeting multiple FPGAs
daisy chained together. When utilizing the advanced
features for the XQF32P Platform Flash PROM, such as
design revisioning, programming files which span cascaded
PROM devices can only be created for cascaded chains
containing only XQF32P PROMs.
The Platform Flash PROMs are compatible with all of the
existing FPGA device families. A reference list of Xilinx
FPGAs and the respective compatible Platform Flash
PROMs is given in
DS541 (v1.0) November 27, 2006
Product Specification
R
Table
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
2.
www.xilinx.com
Table 2: Xilinx FPGAs and Compatible Platform Flash PROMs
Notes:
1.
2.
Virtex™-5 LX Family
XC5VLX50
XC5VLX330
Virtex-4 LX Family
XC4VLX25
XC4VLX40
XC4VLX200
Virtex-4 FX Family
XC4VFX60
XC4VFX140
Virtex-4 SX Family
XC4VSX55
Virtex-II Pro Family
XC2VP40
XC2VP70
Virtex-II
XC2V2000
XC2V3000
XC2V6000
Virtex-E Family
XCV600E
XCV1000E
XCV2000E
Virtex Family
XCV100
XCV300
XCV600
XCV1000
XC2S200
Assumes compression used.
The largest possible Virtex-II bitstream sizes are specified. Refer
to the UG002, Virtex-II Platform FPGA User Guide for
information on bitgen options which affect bitstream size.
FPGA
(2)
Family
Configuration
Bitstream
12,556,672
79,704,832 XCF32P+XCF32P+XCF32P
12,259,712
51,367,808
21,002,880
47,856,896
22,749,184
15,868,192
26,098,976
10,494,368
21,849,504
10,159,648
7,819,904
7,492,000
3,961,632
6,587,520
1,751,808
3,607,968
6,127,744
1,335,840
781,216
Platform Flash PROM
XCF32P+XCF32P
XCF32P+XCF32P
XCF32P
XCF32P
XCF16P
XCF32P
XCF32P
XCF16P
XCF32P
XQF32P
XQF32P
XQF32P
XCF04S
XCF08P
XCF16P
XCF01S
XCF02S
XCF04S
XCF08P
XCF02S
(1)
2