xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 33

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

Pinouts and Pin Descriptions
XQF32P VO48 Pin Names and Descriptions
The XQF32P Platform Flash PROM is available in the VO48 package.
descriptions for the XQF32P 48-pin VO48 plastic, thin, small outline package (TSOP).
Table 8: XQF32P Pin Names and Descriptions (VO48)
DS541 (v1.0) November 27, 2006
Product Specification
OE/RESET
Pin Name
CEO
CLK
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
R
Scan Order
Boundary
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
01
04
03
02
00
11
10
09
06
05
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Boundary
Function
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data Out
Data In
Data In
Data In
Data In
Scan
D0 is the DATA output pin to provide data for configuring an FPGA in
serial mode.
D0-D7 are the DATA output pins to provide parallel data for configuring a
Xilinx FPGA in SelectMap (parallel) mode.
The D0 output is set to a high-impedance state during ISPEN (when not
clamped).
The D1-D7 outputs are set to a high-impedance state during ISPEN
(when not clamped) and when serial mode is selected for configuration.
The D1-D7 pins can be left unconnected when the PROM is used in serial
mode.
Configuration Clock Input. An internal programmable control bit selects
between the internal oscillator and the CLK input pin as the clock source
to control the configuration sequence. Each rising edge on the CLK input
increments the internal address counter if the CLK input is selected, CE
is Low, OE/RESET is High, BUSY is Low (parallel mode only), and CF is
High.
Output Enable/Reset (Open-Drain I/O).
When Low, this input holds the address counter reset and the DATA and
CLKOUT outputs are placed in a high-impedance state. This is a
bidirectional open-drain pin that is held Low while the PROM completes
the internal power-on reset sequence. Polarity is not programmable.
Chip Enable Input. When CE is High, the device is put into low-power
standby mode, the address counter is reset, and the DATA and CLKOUT
outputs are placed in a high-impedance state.
Configuration Pulse (Open-Drain I/O). As an output, this pin allows the
JTAG CONFIG instruction to initiate FPGA configuration without
powering down the FPGA. This is an open-drain signal that is pulsed Low
by the JTAG CONFIG command. As an input, on the rising edge of CF,
the current design revision selection is sampled and the internal address
counter is reset to the start address for the selected revision. If unused,
the CF pin must be pulled High using an external 4.7 KΩ pull-up to V
Chip Enable Output. Chip Enable Output (CEO) is connected to the CE
input of the next PROM in the chain. This output is Low when CE is Low
and OE/RESET input is High, AND the internal address counter has been
incremented beyond its Terminal Count (TC) value. CEO returns to High
when OE/RESET goes Low or CE goes High.
www.xilinx.com
Pin Description
Table 8
provides a list of the pin names and
CCO
.
(VO48)
48-pin
TSOP
28
29
32
33
43
44
47
48
12
11
13
10
6
33