xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 20

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

Reset and Power-On Reset Activation
At power up, the device requires the V
monotonically rise to the nominal operating voltage within
the specified V
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET is held Low by the PROM. Once the required
supplies have reached their respective POR (Power On
Reset) thresholds, the OE/RESET release is delayed (T
minimum) to allow more margin for the power supplies to
stabilize before initiating configuration. The OE/RESET pin
is connected to an external 4.7 kΩ pull-up resistor and also
to the target FPGA's INIT pin. For systems utilizing
slow-rising power supplies, an additional power monitoring
circuit can be used to delay the target configuration until the
system power reaches minimum operating voltages by
holding the OE/RESET pin Low. When OE/RESET is
I/O Input Voltage Tolerance and Power Sequencing
The I/Os on each re-programmable Platform Flash PROM
are fully 3.3V tolerant. This allows 3V CMOS signals to
connect directly to the inputs without damage. The core
power supply (V
output power supply (V
signals can be applied in any order.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is deasserted (High). In standby mode, the address counter
is reset, CEO is driven High, and the remaining outputs are
placed in a high-impedance state regardless of the state of
the OE/RESET input. For the device to remain in the
low-power standby mode, the JTAG pins TMS, TDI, and
DS541 (v1.0) November 27, 2006
Product Specification
200 µs ramp
V
CCINT
V
V
R
CCPOR
CCPD
CCINT
CCINT
rise time. If the power supply cannot
), JTAG pin power supply (V
CCO
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
), and external 3V CMOS I/O
Figure 13: Platform Flash PROM Power-Up Requirements
T
OER
CCINT
Recommended Operating Range
Delay or Restart
Configuration
power supply to
CCJ
),
www.xilinx.com
OER
T
OER
released, the FPGA’s INIT pin is pulled High allowing the
FPGA's configuration sequence to begin. If the power drops
below the power-down threshold (V
and OE/RESET is again held Low until the after the POR
threshold is reached. OE/RESET polarity is not
programmable. These power-up requirements are shown
graphically in
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET is asserted (Low) or CE is
deasserted (High). The address counter is reset, CEO is
driven High, and the remaining outputs are placed in a
high-impedance state.
Note:
POR threshold and for V
voltage level before releasing OE/RESET.
TDO must not be pulled Low, and TCK must be stopped
(High or Low).
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and is also connected to the
PROM CE pin to enable low-power standby mode, then an
external buffer should be used to drive the LED circuit to
ensure valid transitions on the PROM’s CE pin. If low-power
standby mode is not required for the PROM, then the CE pin
should be connected to ground.
A slow-ramping V
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
V
recommended operating conditions.
CCINT
The XQF32P PROM requires both V
and V
Figure 13, page
CCO
50 ms ramp
CCINT
have reached their
CCO
supply may still
to reach the recommended operating
20.
CCPD
T
RST
CCINT
), the PROM resets
TIME (ms)
DS541_13_111706
to rise above its
20