xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 4

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

IEEE 1149.1 Boundary-Scan (JTAG)
The Platform Flash PROM family is compatible with the IEEE
1149.1 boundary-scan standard and the IEEE 1532
in-system configuration standard. A Test Access Port (TAP)
and registers are provided to support all required boundary
scan instructions, as well as many of the optional
instructions specified by IEEE Std. 1149.1. In addition, the
JTAG interface is used to implement in-system programming
(ISP) to facilitate configuration, erasure, and verification
operations on the Platform Flash PROM device.
page 4
instructions supported in the Platform Flash PROMs. Refer
to the IEEE Std. 1149.1 specification for a complete
description of boundary-scan architecture and the required
and optional instructions.
Instruction Register
The Instruction Register (IR) for the Platform Flash PROM
is connected between TDI and TDO during an instruction
scan sequence. In preparation for an instruction scan
sequence, the instruction register is parallel loaded with a
fixed instruction capture pattern. This pattern is shifted out
Table 4: Platform Flash PROM Boundary Scan Instructions
DS541 (v1.0) November 27, 2006
Product Specification
Notes:
1.
Required Instructions
BYPASS
SAMPLE/PRELOAD
EXTEST
Optional Instructions
CLAMP
HIGHZ
IDCODE
USERCODE
Platform Flash PROM
Specific Instructions
CONFIG
Boundary-Scan Command
Caution!
the JTAG 1149.1 specification. If a temporary pause of a JTAG shift operation is
required, then stop the JTAG TCK clock and maintain the JTAG TAP within the
JTAG Shift-IR or Shift-DR TAP state. Do not transition the XQF32P JTAG TAP
through the JTAG Pause-IR or Pause-DR TAP state to temporarily pause a
JTAG shift operation.
For more information see
lists the required and optional boundary-scan
R
The XQF32P JTAG TAP pause states are not fully compliant with
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
"Initiating FPGA Configuration," page
XQF32P IR[15:0]
(hex)
FFFF
0001
0000
00FA
00FC
00FE
00FD
00EE
Table 4,
Enables BYPASS.
Enables boundary-scan SAMPLE/PRELOAD operation.
Enables boundary-scan EXTEST operation.
Enables boundary-scan CLAMP operation.
Places all outputs in high-impedance state simultaneously.
Enables shifting out 32-bit IDCODE.
Enables shifting out 32-bit USERCODE.
Initiates FPGA configuration by pulsing CF pin Low once (for the XQF32P, this
command also resets the selected design revision based on either the external
REV_SEL[1:0] pins or on the internal design revision selection bits).
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11.
onto TDO (LSB first), while an instruction is shifted into the
instruction register from TDI.
XQF32P Instruction Register (16 bits wide)
The Instruction Register (IR) for the XQF32P PROM is sixteen
bits wide and is connected between TDI and TDO during an
instruction scan sequence. The detailed composition of the
instruction capture pattern is illustrated in
The instruction capture pattern shifted out of the XQF32P
device includes IR[15:0]. IR[15:9] are reserved bits and are
set to a logic 0. The ISC Error field, IR[8:7], contains a 10
when an ISC operation is a success; otherwise a 01 when
an In-System Configuration (ISC) operation fails. The
Erase/Program (ER/PROG) Error field, IR[6:5], contains a
10 when an erase or program operation is a success;
otherwise a 01 when an erase or program operation fails.
The Erase/Program (ER/PROG) Status field, IR[4], contains
a logic 0 when the device is busy performing an erase or
programming operation; otherwise, it contains a logic 1. The
ISC Status field, IR[3], contains logic 1 if the device is
currently in In-System Configuration (ISC) mode; otherwise,
it contains logic 0. The DONE field, IR[2], contains logic 1 if
the sampled design revision has been successfully
programmed; otherwise, a logic 0 indicates incomplete
programming. The remaining bits IR[1:0] are set to 01 as
defined by IEEE Std. 1149.1.
Instruction Description
Table 5, page
(1)
5.
4