xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 5

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

Table 5: XQF32P Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence
Boundary Scan Register
The boundary-scan register is used to control and observe the
state of the device pins during the EXTEST,
SAMPLE/PRELOAD, and CLAMP instructions. Each output
pin on the Platform Flash PROM has two register stages which
contribute to the boundary-scan register, while each input pin
has only one register stage. The bidirectional pins have a total
of three register stages which contribute to the boundary-scan
register. For each output pin, the register stage nearest to TDI
controls and observes the output state, and the second stage
closest to TDO controls and observes the High-Z enable state
of the output pin. For each input pin, a single register stage
controls and observes the input state of the pin. The
bidirectional pin combines the three bits, the input stage bit is
first, followed by the output stage bit and finally the output
enable stage bit. The output enable stage bit is closest to TDO.
See the XQF32P Pin Names and Descriptions Tables in the
"Pinouts and Pin Descriptions," page 33
boundary-scan bit order for all connected device pins, or see
the appropriate BSDL file for the complete boundary-scan bit
order description under the "attribute
BOUNDARY_REGISTER" section in the BSDL file. The bit
assigned to boundary-scan cell 0 is the LSB in the
boundary-scan register, and is the register bit closest to TDO.
Identification Registers
IDCODE Register
The IDCODE is a fixed, vendor-assigned value that is used to
electrically identify the manufacturer and type of the device
being addressed. The IDCODE register is 32 bits wide. The
IDCODE register can be shifted out for examination by using
the IDCODE instruction. The IDCODE is available to any
other system component via JTAG.
The IDCODE register has the following binary format:
where
v = the die version number
f = the PROM family code
a = the specific Platform Flash PROM product ID
c = the Xilinx manufacturer's ID
The LSB of the IDCODE register is always read as logic 1
as defined by IEEE Std. 1149.1. The IDCODE register value
for the XQ32PPlatform Flash PROM is <v>5059093.
Note:
revision code (in hex) and can vary.
DS541 (v1.0) November 27, 2006
Product Specification
TDI →
vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1
The <v> in the IDCODE field represents the device’s
R
Reserved
IR[15:9]
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
ISC Error
IR[8:7]
section for the
ER/PROG
IR[6:5]
Error
www.xilinx.com
ER/PROG
Status
IR[4]
USERCODE Register
The USERCODE instruction gives access to a 32-bit user
programmable scratch pad typically used to supply
information about the device's programmed contents. By
using the USERCODE instruction, a user-programmable
identification code can be shifted out for examination. This
code is loaded into the USERCODE register during
programming of the Platform Flash PROM. If the device is
blank or was not loaded during programming, the
USERCODE register contains FFFFFFFFh.
Customer Code Register
For the XQF32P Platform Flash PROM, in addition to the
USERCODE, a unique 32-byte Customer Code can be
assigned to each design revision enabled for the PROM.
The Customer Code is set during programming, and is
typically used to supply information about the design
revision contents. A private JTAG instruction is required to
read the Customer Code. If the PROM is blank, or the
Customer Code for the selected design revision was not
loaded during programming, or if the particular design
revision is erased, the Customer Code contains all ones.
Platform Flash PROM TAP
Characteristics
The Platform Flash PROM family performs both in-system
programming and IEEE 1149.1 boundary-scan (JTAG)
testing via a single 4-wire Test Access Port (TAP). This
simplifies system designs and allows standard Automatic
Test Equipment to perform both functions. The AC
characteristics of the Platform Flash PROM TAP are
described as follows.
TAP Timing
Figure 3, page 6
signals. These TAP timing characteristics are identical for
both boundary-scan and ISP operations.
ISC Status
IR[3]
shows the timing relationships of the TAP
DONE
IR[2]
IR[1:0]
0 1
→ TDO
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