xcf32pvo48m Xilinx Corp., xcf32pvo48m Datasheet - Page 34

• Manufacturer Part Number: xcf32pvo48m
• Description: < B L Qpro Extended Temperature Platform Flash In-system Programmable Configuration Prom
• Manufacturer: Xilinx Corp.

Table 8: XQF32P Pin Names and Descriptions (VO48) (Continued)
DS541 (v1.0) November 27, 2006
Product Specification
EN_EXT_SEL
REV_SEL0
REV_SEL1
Pin Name
CLKOUT
VCCINT
VCCO
BUSY
VCCJ
GND
DNC
TMS
TDO
TCK
TDI
R
Scan Order
Boundary
31
30
29
12
08
07
QPro Extended Temperature Platform Flash In-System Programmable Configuration PROM
Output Enable
Mode Select
Boundary
Function
Data Out
Data Out
Data In
Data In
Data In
Data In
Data In
Scan
Clock
Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low, the Revision
Enable External Selection Input. When this pin is Low, design revision
selection is controlled by the Revision Select pins. When this pin is High,
design revision selection is controlled by the internal programmable
Revision Select control bits. EN_EXT_SEL has an internal 50KΩ resistive
pull-up to V
Select pins are used to select the design revision to be enabled,
overriding the internal programmable Revision Select control bits. The
Revision Select[1:0] inputs have an internal 50 KΩ resistive pull-up to
V
Busy Input. The BUSY input is enabled when parallel mode is selected
for configuration. When BUSY is High, the internal address counter stops
incrementing and the current data remains on the data pins. On the first
rising edge of CLK after BUSY transitions from High to Low, the data for
the next address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the BUSY input
is disabled. BUSY has an internal 50 KΩ resistive pull-down to GND to
provide a logic 0 to the device if the pin is not driven.
Configuration Clock Output. An internal Programmable control bit
enables the CLKOUT signal, which is sourced from either the internal
oscillator or the CLK input pin. Each rising edge of the selected clock
source increments the internal address counter if data is available, CE is
Low, and OE/RESET is High. Output data is available on the rising edge
of CLKOUT. CLKOUT is disabled if CE is High or OE/RESET is Low. If
decompression is enabled, CLKOUT is parked High when decompressed
data is not ready. When CLKOUT is disabled, the CLKOUT pin is put into
a high-Z state. If CLKOUT is used, then it must be pulled High externally
using a 4.7 KΩ pull-up to V
JTAG Mode Select Input. The state of TMS on the rising edge of TCK
determines the state transitions at the Test Access Port (TAP) controller.
TMS has an internal 50 KΩ resistive pull-up to V
to the device if the pin is not driven.
JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP
controller and all the JTAG test and programming electronics.
JTAG Serial Data Input. This pin is the serial input to all JTAG instruction
and data registers. TDI has an internal 50 KΩ resistive pull-up to V
provide a logic 1 to the device if the pin is not driven.
JTAG Serial Data Output. This pin is the serial output for all JTAG
instruction and data registers. TDO has an internal 50KΩ resistive pull-up
to V
+1.8V Supply. Positive 1.8V supply voltage for internal logic.
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply
voltage connected to the output voltage drivers and input buffers.
+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V supply
voltage connected to the TDO output voltage driver and TCK, TMS, and
TDI input buffers.
Ground
Do Not Connect. (These pins must be left unconnected.)
CCO
CCJ
to provide a logic 1 to the device if the pins are not driven.
to provide a logic 1 to the system if the pin is not driven.
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CCO
to provide a logic 1 to the device if the pin is not driven.
CCO
Pin Description
.
CCJ
to provide a logic 1
CCJ
to
18, 35, 37,
39, 40, 41,
31, 36, 46
4, 15, 34
(VO48)
48-pin
17, 23,
14, 16,
TSOP
38, 45
8, 30,
2, 7,
1, 3,
25
26
27
21
20
19
22
24
42
5
9
34