m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 56

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Figure 2.3.6. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
Setting UARTi transmit/receive control register 0 (i=0 to 3)
Setting UART transmit/receive control register 1 (i=0 to 3)
Setting UARTi transmit/receive mode register (i=0 to 3)
b7
b7
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0
0 0
b7
0 0
Note 1: Set the corresponding port direction register to “0”.
Note 2: UART2 transfer pin (TxD
0
0
0 0 0 1
It cannot be set to CMOS output.
0
b0
b0
b0
UARTi transmit interrupt cause select bit
Data logic select bit
Set to “0” in clock synchronous serial I/O mode
UARTi transmit/receive mode register
UiMR [Address 03A8
UARTi transmit/receive control register 0
UiC0 [Address 03AC
0 : Transmit buffer empty (Tl = 1)
0 : No reverse
UARTi transmit/receive control register 1
UiC1 [Address 03AD
BRG count source select bit
CTS/RTS function select bit
(Valid when bit 4 = “0”)
Transmit register empty flag
CTS/RTS disable bit
Data output select bit (Note 2)
CLK polarity select bit
Transfer format select bit
T
Must be fixed to “001” (Serial I/O mode)
Internal/external clock select bit
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
b1 b0
0 0 : f
0 1 : f
1 0 : f
1 1 : Inhibited
0 : CTS function is selected (Note 1)
0 : Data present in transmit register
1 : No data present in transmit register
0 : CTS/RTS function enabled
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
0 : Transmission data is output at falling edge
0 : LSB first
Usually set to “0”
0 : Internal clock
X
D, R
(during transmission)
(transmission completed)
of transfer clock and reception data is input
at rising edge
Continued to the next page
1
8
32
X
is selected
is selected
D I/O polarity reverse bit
is selected
2
: P7
16
16
0
16
, 368
and SCL
, 36C
, 36D
16
16
16
, 0338
, 033C
, 033D
2
: P7
16
1
16
16
) is N-channel open drain output.
, 328
, 32C
, 32D
16
16
16
]
]
]
2. Clock-Synchronous Serial I/O