m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 192

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(1) Related Registers
•OUT_BUF_STS1, OUT_BUF_STS0 flags
•OVER_RUN flag
•FORCE_STALL flag
•DATA_ERR flag
•CLR_OUT_BUF_RDY bit
•CLR_OVER_RUN bit
•CLR_FORCE_STALL bit
•CLR_DATA_ERR bit
USB endpoint x(x=1 to 4) OUT control and status register
These flags indicate OUT FIFO state.
At the time of reading the receive data from the host PC, read these flags to confirm the OUT FIFO
state. When the OUT_BUF_STS1 and the OUT_BUF_STS0 flags are respectively set to “00
are no data in OUT FIFO. When they are respectively set to “10
double buffer. (Invalid for single buffer.) When they are respectively set to “11
data in single buffer while there are two buffer data in double buffer. When they are respectively set
to “01
These flags are updated when one of the following events occurs:
- One valid buffer data is successfully received from the host.
- One buffer data is successfully fetched from OUT FIFO.
- The OUT FIFO buffer data are flushed. (When FLUSH bit is set to “1”.)
This flag indicates occurrence of an overrun in isochronous transfer. The bit is valid only in isochro-
nous transfer. When OUT FIFO is not empty and disables receiving at start of the OUT token from
the host CPU, occurrence of an overrun is recognized, setting this bit to “1”.
Clear this flag by writing “1” to CLR_OVER_RUN bit.
This flag indicates occurrence of a packet size error.
When the data packet, which size exceeds USB endpoint x OUT MAXP register value, is transmitted
from the host CPU, this flag becomes “1”. While this bit is set to “1”, the USB function control unit
does not receive packet data. If it is in bulk transfer, also, STALL handshake is transmitted to the host
CPU.
Clear this flag by writing “1” to CLR_FORCE_STALL bit.
This flag indicates occurrence of data error in isochronous transfer. The bit is valid only in isochro-
nous transfer. If any bit stuffing error or CRC error is detected in the received packet, this flag be-
comes “1”.
Clear this flag by writing “1” to CLR_DATA_ERR bit.
This bit controls OUT FIFO. Set this bit to “1” after one receive buffer data is read from OUT FIFO.
Completion of one buffer data fetch is notified to the USB function control unit and, simultaneously,
the OUT_BUF_STS0 and OUT_BUF_STS1 flags are updated.
When the AUTO_CLR function is enabled, this bit does not need to be set up.
The OVER_RUN flag is cleared to “0” by setting “1” to this bit.
The FORCE_STALL flag is cleared to “0” by setting “1” to this bit.
The DATA_ERR flag is cleared to “0” by setting “1” to this bit.
CLR_OUT_BUF_RDY bit is set to “1” after read of one receive data from OUT FIFO completes.
(When the AUTO_CLR function is enabled, these flags are updated without CLR_OUT_BUF_RDY
bit being set to “1”.)
2
”, it is invalid.
page 183 of 354
2
”, there are only one buffer data in
2
”, there are one buffer
2. USB function
2
”, there