m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 206

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
•CLR_UNDER_RUN bit
•TOGGLE_INIT bit
•FLUSH bit
•INTPT bit
•ISO bit
•SEND_STALL bit
The UNDER_RUN flag is cleared to “0” by setting “1” to this bit.
This bit initializes data toggle bit required in bulk and interrupt transfer.
When initialization of the data toggle sequence is requested from the host CPU at the time of configu-
ration, etc., set this bit to “1” before starting the IN endpoint communication and initialize PID to
DATA0. At this time, the internal read/write pointer of IN FIFO is also initialized.
This bit controls the IN FIFO packet.
Read the IN_BUF_STS1 and IN_BUF_STS0 flags and confirm that there are data in the IN FIFO,
and then, set this bit to “1”. When the IN FIFO is flushed, the IN_BUF_STS1 and IN_BUF_STS0 flags
are updated as follows:
The transmit data may be destroyed if this bit is set to “1” during USB transfer.
On completing one buffer data flush, this bit is automatically cleared to “0”.
This bit controls transfer mode in interrupt transfer. Only when using the IN endpoint for the rate
feedback interrupt transfer, set this bit to “1”.
With this bit being set to “1”, when an IN token is received from the host CPU, IN FIFO data are
transmitted regardless of the IN_BUF_STS1 and IN_BUF_STS0 flag states or the data toggle.
Fix this bit at “0” for isochronous transfer, bulk transfer, and normal interrupt transfer.
This bit controls isochronous transfer. With this bit being set to “1”, the IN endpoint is used for isoch-
ronous transfer. Fix this bit at “0” for bulk transfer and interrupt transfer.
This bit controls the STALL response to the host CPU.
Set this bit to “1” when the IN endpoint is in STALL state. While this bit is set to “1”, the USB function
control unit transmits the STALL handshake concerning all the IN transactions to the host CPU.
When the IN endpoint has returned from STALL state, write “0” to clear this bit. The IN endpoint
communication is resumed.
- When there is one buffer data in IN FIFO, the IN FIFO becomes empty.
- When two buffer data exist in IN FIFO, the older data is flushed.
At this time, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated to “00
At this time, the IN_BUF_STS1 and IN_BUF_STS0 flags are updated to “01
one more buffer data is left inside the IN FIFO.)
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2. USB function