m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 180

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
• SETUP_END flag
• CLR_OUT_BUF_RDY bit
• SET_IN_BUF_RDY bit
• CLR_SETUP bit
Except for when an incorrect data toggle is received in the SETUP stage, on occurrence of the above
condition, STALL is transmitted to the IN/OUT token with a problem. When an incorrect data toggle
is received in the SETUP stage, ACK is returned to the SETUP stage and STALL is returned to next
IN/OUT token.
The STALL handshake occurring by the above condition completes the control transfer in operation
by being transmitted to one transaction. The packet after STALL handshake is regarded as the start
of new control transfer. Set this flag to “0” by writing “1” to CLR_FORCE_STALL bit.
This flag shows the interrupt in control transfer.
This flag is set to “1” when at least one of the following conditions occurs:
When this flag is set to “1” and transmit data to the host CPU exists, IN_BUF_RDY bit is cleared to “0”
and the IN FIFO data is destroyed. Discontinue access to FIFO and process the preceding setup.
Also, when a new SETUP packet is received right after the SETUP_END flag is set to “1” (when the
next new SETUP packet is received before the data phase or the status phase is completed), the
SETUP flag and the OUT_BUT_RDY flag in addition to the SETUP_END flag are set to “1”, indicat-
ing that a new SETUP packet data exists in OUT FIFO.
Set the SETUP_END flag to “0” by writing “1” to CLR_SETUP_END bit.
This bit controls clearing of the OUT_BUF_RDY flag.
This bit is set to “1” after reading the data packet from OUT FIFO. When this flag is written to “1”, the
OUT_BUF_RDY flag is cleared to “0”.
When the OUT_BUF_RDY flag is set to “1” by receiving the SETUP token, the USB function control
unit responds with NAK to the data request from the host CPU.
Until decoding of request data from the host CPU is completed, do not set this bit to “1” (nor the
OUT_BUF_RDY flag is set to “0”.)
This bit controls setting of the IN_BUF_RDY flag to “1”.
Completion of one buffer data write is notified to the USB function control unit.
Set this bit to “1” after writing the data packet to IN FIFO. When this bit is written to “1”, the
IN_BUF_RDY flag is set to “1”.
This bit controls clearing of the SETUP flag.
Set this bit to “1” after decoding the SETUP packet. When this bit is written to “1”, the SETUP flag is
cleared to “0”.
- Data exceeding the one specified in the SETUP stage are required. (An OUT token is received
- Data exceeding the one specified are received in USB endpoint 0 MAXP register.
- Transmission of the data which had amount of data set by setup phase during data phase process-
- A new SETUP packet is received before status phase is completed.
after the DATA_END flag is set.)
ing is completed. (The status phase is started before the DATA_END flag is set.)
page 171 of 354
2. USB function