m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 332

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Figure 3.8.3. Set-up procedure of controlling power using stop mode (1)
b 7
S e t t i n g o p e r a t i o n c l o c k a f t e r r e t u r n i n g f r o m s t o p m o d e
b 7
0
b7
b7
S e t t i n g i n t e r r u p t e x c e p t s t o p m o d e c a n c e l
b7
I n i t i a l c o n d i t i o n
Canceling protect
b 7
( W h e n o p e r a t i n g w i t h X
As this register becomes setting mentioned above when
operating with X
the user does not need to set it again.
When operating with X
to “0” before setting system clock select bit to “0”. The both
bits cannot be set at the same time.
I
n t e r r u p t c o n t r o l r e g i s t e r S i R I C ( i = 0 , 2 , 3 ) [ A d d r e s s 0 0 4 A
0
1
0
0
0
IN
0
0
0
(count source of BCLK is X
0
0
0
0
page 323 of 354
b 0
CIN
b0
0
b 0
1
0
b 0
b 0
b 0
0
0
I N
, set main clock (X
I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t
Reserved bit
M a i n c l o c k ( X
S 1 3 B C N I C
T A i I C ( i = 0 t o 4 ) [ A d d r e s s 0 0 5 4
E P 0 I C
A D I C
D M i I C ( i = 0 t o 3 ) [ A d d r e s s 0 0 4 C
S i T I C ( i = 0 t o 3 ) [ A d d r e s s 0 0 5 3
S U S P I C
R S M I C
R S T I C
S O F I C
V B D I C
U S B F I C
S y s t e m c l o c k s e l e c t b i t
System clock control register 0
CM0
P 1 0
K e y s c a n i n p u t p o r t
K e y s c a n d a t a
0 0 0 : I n t e r r u p t d i s a b l e d
Must always be set to “0”
a f t e r r e t u r n i n g )
X
P u l l - u p c o n t r o l r e g i s t e r 2
[ A d d r e s s 0 3 F E
P U R 2
P o r t P 1 0 d i r e c t i o n r e g i s t e r
[ A d d r e s s 0 3 F 6
P D 0
P o r t P 0 r e g i s t e r
[ A d d r e s s 0 3 E 0
P 0
O n
Protect register [Address 000A
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
and frequency synthesizer registers (addresses 03DB
I N
1 : Write-enabled
0
, X
t o P 1 0
O U T
[Address 0006
3
I N
p u l l e d h i g h
- X
1 6
1 6
1 6
[ A d d r e s s 0 0 4 3
[ A d d r e s s 0 0 4 6
[ A d d r e s s 0 0 4 B
[ A d d r e s s 0 0 5 6
[ A d d r e s s 0 0 5 8
[ A d d r e s s 0 0 5 A
[ A d d r e s s 0 0 5 B
[ A d d r e s s 0 0 5 C
[ A d d r e s s 0 0 5 D
O U T
IN
]
]
]
IN
-X
),
) s t o p b i t
OUT
16
]
) stop bit
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
1 6
C o n t i n u e d t o t h e n e x t p a g e
]
16
]
, 0 0 4 5
, 0 0 5 1
]
]
, 0 0 4 2
]
]
]
, 0 0 4 E
]
]
]
1 6
1 6
1 6
1 6
, 0 0 4 7
, 0 0 4 F
, 0 0 5 5
, 0 0 5 0
M a i n
1 6
1 6
1 6
1 6
As this register becomes setting mentioned above when operating with X
(count source of BCLK is X
When operating with X
clock select bit to “1”. The both bits cannot be set at the same time.
b 7
( W h e n o p e r a t i n g w i t h X
1
b7
b7
b7
, 0 0 5 7
, 0 0 4 D
]
, 0 0 5 2
Processor interrupt priority level (IPL) = 0
Interrupt enable flag (I) =0
1 6
16
1 6
1 6
0
, 0 0 5 9
]
]
to 03DF
1
1
1 6
]
0
16
0
1
)
0
0
IN
1
0
, set port Xc select bit to “1” before setting system
b 0
b0
0
0
b0
b 0
1
1
C I N
CIN
16
Reserved bit
I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t
R e s e r v e d b i t
INTiIC(i=0 to 2) [Address 005F
S1RIC
S02BCNIC
Interrupt priority level select bit
Must always be set to “0”
K e y s c a n o u t p u t p o r t
Port X
0 0 0 : I n t e r r u p t d i s a b l e d
M u s t a l w a y s b e s e t t o “ 0 ”
S y s t e m c l o c k s e l e c t b i t
), the user does not need to set it again.
System clock control register 0
CM0 [Address 0006
and 0007
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e r
[ A d d r e s s 0 0 4 1
K U P I C
a f t e r r e t u r n i n g )
X
Port P0 direction register
[Address 03E2
PD0
Set higher value than the present IPL
X
C I N
CIN
, X
C
-X
3. Controlling Power Applications
select bit
COUT
C O U T
16
)
generation
1 6
[Address 0048
[Address 0049
16
]
]
16
]
16
16
16
, 0044
]
]
16
, 005E
CIN
16
]