w83627sf Winbond Electronics Corp America, w83627sf Datasheet - Page 69

• Manufacturer Part Number: w83627sf
• Description: Winbond I/o
• Manufacturer: Winbond Electronics Corp America

5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode.
Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, will
go to legacy UART mode and clear some register values shown table as follows.
TABLE :BAUD RATE TABLE
Note 1: Only use in high speed mode, when Bank0.Reg6.Bit7 is set.
** The percentage error for all baud rates, except where indicated otherwise, is 0.16%
Desired Baud Rate
115200
19200
57600
134.5
38400
1200
1800
2000
2400
3600
4800
7200
9600
1.5M
110
150
300
600
50
75
BAUD RATE USING 24 MHZ TO GENERATE 1.8461 MHZ
Decimal divisor used to
generate 16X clock
2304
1536
1047
1
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
Note 1
- 62 -
Publication Release Date: Nov. 2000
Percent error difference between
desired and actual
0.099%
0.18%
0.53%
0%
PRELIMINARY
W83627SF
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
Revision 0.60